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AgeCommit message (Expand)AuthorFilesLines
2019-03-06migration: Add an ability to ignore shared RAM blocksYury Kotov1-1/+0
2019-03-06exec: Change RAMBlockIterFunc definitionYury Kotov1-2/+4
2019-03-04Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell1-1/+0
2019-02-21include/exec/helper-head.h: support "const void *" in helper callsDavid Hildenbrand1-0/+5
2019-02-21vhost-net: compile it on all targets that have virtio-net.Paolo Bonzini1-1/+0
2019-02-11exec-all: document that tlb_fill can trigger a TLB resizeEmilio G. Cota1-0/+5
2019-02-07Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190206' into stagingPeter Maydell1-0/+4
2019-02-06accel/tcg: Consider cluster index in tb_lookup__cpu_state()Peter Maydell1-0/+4
2019-02-05Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell3-16/+16
2019-02-05exec: Add target-specific tlb bits to MemTxAttrsRichard Henderson1-0/+10
2019-02-05unify len and addr type for memory/address APIsLi Zhijian3-16/+16
2019-01-29accel/tcg: Add cluster number to TCG TB hashPeter Maydell1-1/+3
2019-01-29memory: add memory_region_flush_rom_device()Stefan Hajnoczi1-0/+18
2019-01-28cputlb: Remove static tlb sizingRichard Henderson2-60/+0
2019-01-28tcg: introduce dynamic TLB sizingEmilio G. Cota2-2/+76
2019-01-11qemu/queue.h: simplify reverse access to QTAILQPaolo Bonzini1-1/+1
2019-01-11qemu/queue.h: leave head structs anonymous unless necessaryPaolo Bonzini1-2/+2
2018-12-26tcg: Add TCG_CALL_NO_RETURNRichard Henderson2-7/+27
2018-12-26exec: Add RISC-V GCC poison macroAlistair Francis1-0/+1
2018-12-17Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20181216' into stagingPeter Maydell2-103/+2
2018-12-17include: move exec/tb-hash-xx.h to qemu/xxhash.hEmilio G. Cota2-123/+1
2018-12-17exec: introduce qemu_xxhash{2,4,5,6,7}Emilio G. Cota2-11/+32
2018-12-14Rename cpu_physical_memory_write_rom() to address_space_write_rom()Peter Maydell2-2/+26
2018-11-06memory: learn about non-volatile memory regionMarc-André Lureau1-0/+25
2018-10-31cputlb: Remove tlb_c.pending_flushesRichard Henderson1-6/+0
2018-10-31cputlb: Filter flushes on already clean tlbsRichard Henderson1-1/+6
2018-10-31cputlb: Count "partial" and "elided" tlb flushesRichard Henderson2-3/+11
2018-10-31cputlb: Move env->vtlb_index to env->tlb_d.vindexRichard Henderson1-2/+3
2018-10-31cputlb: Split large page tracking per mmu_idxRichard Henderson1-2/+12
2018-10-31cputlb: Move cpu->pending_tlb_flush to env->tlb_c.pending_flushRichard Henderson1-1/+7
2018-10-31cputlb: Move tlb_lock to CPUTLBCommonRichard Henderson1-3/+14
2018-10-30Merge remote-tracking branch 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-...Peter Maydell1-3/+3
2018-10-26memory.h: fix typos in commentsLi Qiang1-3/+3
2018-10-25target/mips: Add disassembler support for nanoMIPSAleksandar Markovic1-0/+1
2018-10-19Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-2/+2
2018-10-19Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20181018' into stagingPeter Maydell4-16/+50
2018-10-19target-i386 : add coalesced_pio APIPeng Hao1-2/+2
2018-10-19COLO: Load dirty pages into SVM's RAM cache firstlyZhang Chen1-0/+1
2018-10-18cputlb: read CPUTLBEntry.addr_write atomicallyEmilio G. Cota2-2/+11
2018-10-18tcg: Add tlb_index and tlb_entry helpersRichard Henderson2-15/+29
2018-10-18cputlb: serialize tlb updates with env->tlb_lockEmilio G. Cota1-0/+3
2018-10-18exec: introduce tlb_initEmilio G. Cota1-0/+8
2018-10-02memory: Remove old_mmio accessorsPeter Maydell1-5/+0
2018-10-02hostmem-file: make available memory-backend-file on POSIX-based hostsHikaru Nishida1-1/+1
2018-08-28ppc: Remove deprecated ppcemb targetThomas Huth1-1/+0
2018-08-21Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-3.1-pull-re...Peter Maydell2-11/+24
2018-08-21Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell2-4/+55
2018-08-20memory: Remove MMIO request_ptr APIsPeter Maydell1-35/+0
2018-08-17linux-user: fix 32bit g2h()/h2g()Laurent Vivier2-11/+24
2018-08-14accel/tcg: Check whether TLB entry is RAM consistently with how we set it upPeter Maydell1-2/+0
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