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2021-03-07esp: latch individual bits in ESP_RINTR registerMark Cave-Ayland1-16/+13
Currently the ESP_RINTR register is set to a specific value as required within the ESP state machine. In order to implement the upcoming deferred interrupt functionality it is necessary to set individual bits within ESP_RINTR so that a deferred interrupt will not overwrite the value of any other interrupt bits. This also requires fixing up a few locations where the ESP_RINTR and ESP_RSEQ registers are set/reset unexpectedly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-33-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: implement FIFO flush commandMark Cave-Ayland1-0/+2
At this point it is now possible to properly implement the FIFO flush command without causing guest errors. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-32-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: add 4 byte PDMA read and write transfersMark Cave-Ayland1-2/+4
The MacOS toolbox ROM performs 4 byte reads/writes when transferring data to and from the target. Since the SCSI bus is 16-bits wide, use the memory API to split a 4 byte access into 2 x 2 byte accesses. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-31-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: remove pdma_origin from ESPStateMark Cave-Ayland1-66/+8
Now that all data is transferred via the FIFO (ti_buf) there is no need to track the source buffer being used for the data transfer. This also eliminates the need for a separate subsection for PDMA state migration. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-30-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: use FIFO for PDMA transfers between initiator and deviceMark Cave-Ayland1-34/+75
PDMA as implemented on the Quadra 800 uses DREQ to load data into the FIFO up to a maximum of 16 bytes at a time. The MacOS toolbox ROM requires this because it mixes FIFO and PDMA transfers whilst checking the FIFO status and counter registers to ensure success. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-29-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: fix PDMA target selectionMark Cave-Ayland1-19/+34
Currently the target selection for PDMA is done after the SCSI command has been delivered which is not correct. Perform target selection as part of the initial get_cmd() call when the command is submitted: if no target is present, don't raise DRQ. If the target is present then switch to the command phase since the MacOS toolbox ROM checks for this before attempting to submit the SCSI command. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-28-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: rename get_cmd_cb() to esp_select()Mark Cave-Ayland1-5/+5
This better describes the purpose of the function. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-27-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: remove CMD pdma_originMark Cave-Ayland1-10/+12
The cmdbuf is really just a copy of FIFO data (including extra message phase bytes) so its pdma_origin is effectively TI. Fortunately we already know when we are receiving a SCSI command since do_cmd == 1 which enables us to distinguish between the two cases in esp_pdma_read()/esp_pdma_write(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-26-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: use in-built TC to determine PDMA transfer lengthMark Cave-Ayland1-15/+13
Real hardware simply counts down using the in-built TC to determine when the the PDMA request is complete. Use the TC to determine the PDMA transfer length which then enables us to remove the redundant pdma_len variable. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-25-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: use ti_wptr/ti_rptr to manage the current FIFO position for PDMAMark Cave-Ayland1-15/+8
This eliminates the last user of the PDMA-specific pdma_cur variable which can now be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-24-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: move PDMA length adjustments into esp_pdma_read()/esp_pdma_write()Mark Cave-Ayland1-10/+14
Here the updates to async_len and ti_size are moved into the corresponding esp_pdma_read()/esp_pdma_write() function to eliminate the reference to pdma_cur in do_dma_pdma_cb(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-23-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: remove redundant pdma_start from ESPStateMark Cave-Ayland1-17/+2
Now that PDMA SCSI commands are accumulated in cmdbuf in the same way as normal commands, the existing logic for locating the start of the SCSI command in cmdbuf via cmdlen can be used. This enables the PDMA-specific pdma_start and also get_pdma_buf() to be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-22-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: remove the buf and buflen parameters from get_cmd()Mark Cave-Ayland1-5/+6
Now that all SCSI commands are accumulated in cmdbuf, remove the buf and buflen parameters from get_cmd() since these always reference cmdbuf and ESP_CMDBUF_SZ respectively. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-21-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: remove buf parameter from do_cmd()Mark Cave-Ayland1-6/+7
Now that all SCSI commands are accumulated in cmdbuf, remove the buf parameter from do_cmd() since this always points to cmdbuf. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-20-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: accumulate SCSI commands for PDMA transfers in cmdbuf instead of pdma_bufMark Cave-Ayland1-31/+25
ESP SCSI commands are already accumulated in cmdbuf and so there is no need to keep a separate pdma_buf buffer. Accumulate SCSI commands for PDMA transfers in cmdbuf instead of pdma_buf so update cmdlen accordingly and change pdma_origin for PDMA transfers to CMD which allows the PDMA origin to be removed. This commit also removes a stray memcpy() from get_cmd() which is a no-op because cmdlen is always zero at the start of a command. Notionally the removal of pdma_buf from vmstate_esp_pdma also breaks migration compatibility for the PDMA subsection until its complete removal by the end of the series. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-19-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: move pdma_len and TC logic into esp_pdma_read()/esp_pdma_write()Mark Cave-Ayland1-18/+32
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-18-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: use pdma_origin directly in esp_pdma_read()/esp_pdma_write()Mark Cave-Ayland1-6/+28
This is the first step in removing get_pdma_buf() from esp.c. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-17-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: introduce esp_pdma_read() and esp_pdma_write() functionsMark Cave-Ayland1-8/+20
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-16-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: remove minlen restriction in handle_tiMark Cave-Ayland1-10/+2
The limiting of DMA transfers to the maximum size of the available data is already handled by esp_do_dma() and do_dma_pdma_cb(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-15-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: remove dma_left from ESPStateMark Cave-Ayland1-16/+31
The ESP device already keeps track of the remaining bytes left to transfer via its TC (transfer counter) register which is decremented for each byte that is transferred across the SCSI bus. Switch the transfer logic to use the value of TC instead of dma_left and then remove dma_left completely, adding logic to the vmstate_esp post_load() function to transfer the old dma_left value to the TC register during migration from older versions. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-14-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: remove dma_counter from ESPStateMark Cave-Ayland1-3/+1
The value of dma_counter is set once at the start of the transfer and remains the same until the transfer is complete. This allows the check in esp_transfer_data to be simplified since dma_left will always be non-zero until the transfer is completed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-13-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: apply transfer length adjustment when STC is zero at TC load timeMark Cave-Ayland1-4/+5
Perform the length adjustment whereby a value of 0 in the STC represents a transfer length of 0x10000 at the point where the TC is loaded at the start of a DMA command rather than just when a TI (Transfer Information) command is executed. This better matches the description as given in the datasheet. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-12-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: introduce esp_get_stc()Mark Cave-Ayland1-3/+12
This function simplifies reading the STC register value without having to manually shift each individual 8-bit value. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-11-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: introduce esp_get_tc() and esp_set_tc()Mark Cave-Ayland1-15/+23
These functions simplify reading and writing the TC register value without having to manually shift each individual 8-bit value. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-10-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: determine transfer direction directly from SCSI phaseMark Cave-Ayland1-3/+2
The transfer direction is currently determined by checking the sign of ti_size but as this series progresses ti_size can be zero at the end of the transfer. Use the SCSI phase to determine the transfer direction as used in other SCSI controller implementations. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-9-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: add PDMA trace eventsMark Cave-Ayland2-0/+10
This will become more useful later when trying to debug mixed FIFO and PDMA requests. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-8-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: fix esp_reg_read() trace eventMark Cave-Ayland1-6/+12
Move the trace event to the end of the function so that it correctly reports the returned value if it doesn't come directly from the rregs array. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-7-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: add trace event when receiving a TI commandMark Cave-Ayland2-0/+2
This enables us to determine whether the command being issued is for a DMA or a non-DMA transfer. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-6-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: add vmstate_esp version to embedded ESPStateMark Cave-Ayland2-3/+23
The QOM object representing ESPState is currently embedded within both the SYSBUS_ESP and PCI_ESP devices with migration state handled by embedding vmstate_esp within each device using VMSTATE_STRUCT. Since the vmstate_esp fields are embedded directly within the migration stream, the incoming vmstate_esp version_id is lost. The only version information available is that from vmstate_sysbus_esp_scsi and vmstate_esp_pci_scsi, but those versions represent their respective devices and not that of the underlying ESPState. Resolve this by adding a new version-dependent field in vmstate_sysbus_esp_scsi and vmstate_esp_pci_scsi which stores the vmstate_esp version_id field within ESPState to be used to allow migration from older QEMU versions. Finally bump the vmstate_esp version to 5 to cover the upcoming ESPState changes within this patch series. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-5-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: QOMify the internal ESP device stateMark Cave-Ayland2-20/+77
Make this new QOM device state a child device of both the sysbus-esp and esp-pci implementations. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-4-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: rename existing ESP QOM type to SYSBUS_ESPMark Cave-Ayland5-11/+11
The existing ESP QOM type currently represents a sysbus device with an embedded ESP state. Rename the type to SYSBUS_ESP accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-3-mark.cave-ayland@ilande.co.uk>
2021-03-07esp: checkpatch fixesMark Cave-Ayland1-21/+31
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-2-mark.cave-ayland@ilande.co.uk>
2021-03-05Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210305' ↵Peter Maydell4-14/+28
into staging some accumulated s390x fixes # gpg: Signature made Fri 05 Mar 2021 15:50:00 GMT # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck-gitlab/tags/s390x-20210305: target/s390x/kvm: Simplify debug code vfio-ccw: Do not read region ret_code after write css: SCHIB measurement block origin must be aligned virtio-ccw: commands on revision-less devices s390x/pci: restore missing Query PCI Function CLP data hw/s390x: fix build for virtio-9p-ccw target/s390x/arch_dump: Fix warning for the name field in the PT_NOTE section s390x/cpu_model: disallow unpack for --only-migratable Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05Merge remote-tracking branch ↵Peter Maydell13-55/+589
'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging RISC-V PR for 6.0 This PR is a collection of RISC-V patches: - Improvements to SiFive U OTP - Upgrade OpenSBI to v0.9 - Support the QMP dump-guest-memory - Add support for the SiFive SPI controller (sifive_u) - Initial RISC-V system documentation - A fix for the Goldfish RTC - MAINTAINERS updates - Support for high PCIe memory in the virt machine # gpg: Signature made Thu 04 Mar 2021 14:44:31 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210304: hw/riscv: virt: Map high mmio for PCIe hw/riscv: virt: Limit RAM size in a 32-bit system hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() hw/riscv: Drop 'struct MemmapEntry' MAINTAINERS: Add a SiFive machine section goldfish_rtc: re-arm the alarm after migration docs/system: riscv: Add documentation for sifive_u machine docs/system: Add RISC-V documentation docs/system: Sort targets in alphabetical order hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card hw/riscv: sifive_u: Add QSPI0 controller and connect a flash hw/ssi: Add SiFive SPI controller support hw/block: m25p80: Add various ISSI flash information hw/block: m25p80: Add ISSI SPI flash support target-riscv: support QMP dump-guest-memory roms/opensbi: Upgrade from v0.8 to v0.9 hw/misc: sifive_u_otp: Use error_report() when block operation fails target/riscv: Declare csr_ops[] with a known size Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-04hw/riscv: virt: Map high mmio for PCIeBin Meng1-2/+33
Some peripherals require 64-bit PCI address, so let's map the high mmio space for PCIe. For RV32, the address is hardcoded to below 4 GiB from the highest accessible physical address. For RV64, the base address depends on top of RAM and is aligned to its size which is using 16 GiB for now. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng1-0/+10
RV32 supports 34-bit physical address hence the maximum RAM size should be limited. Limit the RAM size to 10 GiB, which leaves some room for PCIe high mmio space. For 32-bit host, this is not needed as machine->ram_size cannot represent a RAM size that big. Use a #if size test to only do the size limitation for the 64-bit host. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng1-7/+7
`link_up` is never used in gpex_pcie_init(). Drop it. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng6-37/+19
There is already a MemMapEntry type defined in hwaddr.h. Let's drop the RISC-V defined `struct MemmapEntry` and use the existing one. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210220144807.819-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04goldfish_rtc: re-arm the alarm after migrationLaurent Vivier1-0/+2
After a migration the clock offset is updated, but we also need to re-arm the alarm if needed. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201220112615.933036-7-laurent@vivier.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng2-2/+42
This adds the QSPI2 controller to the SoC, and connects an SD card to it. The generation of corresponding device tree source fragment is also added. Specify machine property `msel` to 11 to boot the same upstream U-Boot SPL and payload image for the SiFive HiFive Unleashed board. Note subsequent payload is stored in the SD card image. $ qemu-system-riscv64 -nographic -M sifive_u,msel=11 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=sdcard.img,if=sd Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-6-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng2-0/+54
This adds the QSPI0 controller to the SoC, and connects an ISSI 25WP256 flash to it. The generation of corresponding device tree source fragment is also added. Since the direct memory-mapped mode is not supported by the SiFive SPI model, the <reg> property does not populate the second group which represents the memory mapped address of the SPI flash. With this commit, upstream U-Boot for the SiFive HiFive Unleashed board can boot on QEMU 'sifive_u' out of the box. This allows users to develop and test the recommended RISC-V boot flow with a real world use case: ZSBL (in QEMU) loads U-Boot SPL from SPI flash to L2LIM, then U-Boot SPL loads the payload from SPI flash that is combined with OpenSBI fw_dynamic firmware and U-Boot proper. Specify machine property `msel` to 6 to allow booting from the SPI flash. U-Boot spl is directly loaded via `-bios`, and subsequent payload is stored in the SPI flash image. Example command line: $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=spi-nor.img,if=mtd Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/ssi: Add SiFive SPI controller supportBin Meng3-0/+363
This adds the SiFive SPI controller model for the FU540 SoC. The direct memory-mapped SPI flash mode is unsupported. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/block: m25p80: Add various ISSI flash informationBin Meng1-0/+13
This updates the flash information table to include various ISSI flashes that are supported by upstream U-Boot and Linux kernel. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/block: m25p80: Add ISSI SPI flash supportBin Meng1-1/+43
This adds the ISSI SPI flash support. The number of dummy cycles in fast read, fast read dual output and fast read quad output commands is currently using the default 8. Likewise, the same default value is used for fast read dual/quad I/O command. Per the datasheet [1], the number of dummy cycles is configurable, but this is not modeled at present. For flash whose size is larger than 16 MiB, the sequence of 3-byte address along with EXTADD bit in the bank address register (BAR) is not supported. We assume that guest software always uses op codes with 4-byte address sequence. Fortunately, this is the case for both U-Boot and Linux spi-nor drivers. QPI (Quad Peripheral Interface) that supports 2-cycle instruction has different default values for dummy cycles of fast read family commands, and is unsupported at the time being. [1] http://www.issi.com/WW/pdf/25LP-WP256.pdf Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/misc: sifive_u_otp: Use error_report() when block operation failsBin Meng1-8/+5
At present when blk_pread() / blk_pwrite() fails, a guest error is logged, but this is not really a guest error. Change to use error_report() instead. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1611026585-29971-1-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04Merge remote-tracking branch 'remotes/kraxel/tags/ui-20210304-pull-request' ↵Peter Maydell4-22/+6
into staging ui/console: message surface tweaks. ui/cocoa: bugfixes and cleanups. # gpg: Signature made Thu 04 Mar 2021 08:36:53 GMT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20210304-pull-request: virtio-gpu: Do not distinguish the primary console ui/console: Pass placeholder surface to displays ui/console: Add placeholder flag to message surface ui/cocoa: Replace fprintf with error_report configure: Improve OpenGL dependency detections ui/cocoa: Fix stride resolution of pixman image ui/gtk: vte: fix sending multiple characeters ui/cocoa: Remove the uses of full screen APIs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-04vfio-ccw: Do not read region ret_code after writeEric Farman1-6/+6
A pwrite() call returns the number of bytes written (or -1 on error), and vfio-ccw compares this number with the size of the region to determine if an error had occurred or not. If they are not equal, this is a failure and the errno is used to determine exactly how things failed. An errno of zero is possible (though unlikely) in this situation and would be translated to a successful operation. If they ARE equal, the ret_code field is read from the region to determine how to proceed. While the kernel sets the ret_code field as necessary, the region and thus this field is not "written back" to the user. So the value can only be what it was initialized to, which is zero. So, let's convert an unexpected length with errno of zero to a return code of -EFAULT, and explicitly set an expected length to a return code of zero. This will be a little safer and clearer. Suggested-by: Matthew Rosato <mjrosato@linux.ibm.com> Signed-off-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20210303160739.2179378-1-farman@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-03-04virtio-ccw: commands on revision-less devicesCornelia Huck1-7/+14
The virtio standard specifies that any non-transitional device must reject commands prior to revision setting (which we do). Devices that are transitional need to assume revision 0 (legacy) if the driver sends a non-revision-setting command first in order to support legacy drivers. We neglected to do the latter. Fortunately, nearly everything worked as intended anyway; the only problem was not properly rejecting revision setting after some other command had been issued. Easy to fix by setting revision to 0 if we see a non-revision command on a legacy-capable revision-less device. Found by code inspection, not observed in the wild. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Halil Pasic <pasic@linux.ibm.com> Message-Id: <20210216111830.1087847-1-cohuck@redhat.com>
2021-03-04s390x/pci: restore missing Query PCI Function CLP dataMatthew Rosato1-0/+5
Some CLP response data was accidentally dropped when fixing endianness issues with the Query PCI Function CLP response. All of these values are sent as 0s to the guest for emulated devices, so the impact is only observed on passthrough devices. Fixes: a4e2fff1b104 ("s390x/pci: fix endianness issues") Signed-off-by: Matthew Rosato <mjrosato@linux.ibm.com> Message-Id: <1613681609-9349-1-git-send-email-mjrosato@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-03-04hw/s390x: fix build for virtio-9p-ccwHalil Pasic1-1/+3
Commit 2c44220d05 ("meson: convert hw/arch*"), which migrated the old Makefile.objs to meson.build accidentally excluded virtio-ccw-9p.c and thus the virtio-9p-ccw device from the build (and potentially also included the file virtio-ccw-blk.c twice in the source set). And since CONFIG_VIRTFS can't be used the way it was used here (see commit 2c9dce0196 ("meson: do not use CONFIG_VIRTFS")), the preconditions have to be written differently. Let's fix this! Signed-off-by: Halil Pasic <pasic@linux.ibm.com> Fixes: 2c44220d05 ("meson: convert hw/arch*") Reported-by: Jakob Naucke <jakob.naucke@ibm.com> Cc: qemu-stable@nongnu.org Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210218034059.1096078-1-pasic@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
generated by cgit v1.1 at 2025-03-28 20:38:47 +0000