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2019-07-04hw/timer/armv7m_systick: Forbid non-privileged accessesPeter Maydell1-6/+20
Like most of the v7M memory mapped system registers, the systick registers are accessible to privileged code only and user accesses must generate a BusFault. We implement that for registers in the NVIC proper already, but missed it for systick since we implement it as a separate device. Correct the omission. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190617175317.27557-6-peter.maydell@linaro.org
2019-07-04target/arm: v8M: Check state of exception being returned fromPeter Maydell1-1/+13
In v8M, an attempt to return from an exception which is not active is an illegal exception return. For this purpose, exceptions which can configurably target either Secure or NonSecure are not considered to be active if they are configured for the opposite security state for the one we're trying to return from (eg attempt to return from an NS NMI but NMI targets Secure). In the pseudocode this is handled by IsActiveForState(). Detect this case rather than counting an active exception possibly of the wrong security state as being sufficient. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190617175317.27557-4-peter.maydell@linaro.org
2019-07-04arm v8M: Forcibly clear negative-priority exceptions on deactivatePeter Maydell1-5/+35
To prevent execution priority remaining negative if the guest returns from an NMI or HardFault with a corrupted IPSR, the v8M interrupt deactivation process forces the HardFault and NMI to inactive based on the current raw execution priority, even if the interrupt the guest is trying to deactivate is something else. In the pseudocode this is done in the Deactivate() function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190617175317.27557-3-peter.maydell@linaro.org
2019-07-04Merge remote-tracking branch 'remotes/awilliam/tags/vfio-fixes-20190702.0' ↵Peter Maydell1-2/+5
into staging VFIO fixes 2019-07-02 - Remove outdated comment (Fabiano Rosas) - Log MSI-X eventfd switch failure, fix Coverity issue (Eric Auger) # gpg: Signature made Tue 02 Jul 2019 23:21:56 BST # gpg: using RSA key 239B9B6E3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" [full] # gpg: aka "Alex Williamson <alex@shazbot.org>" [full] # gpg: aka "Alex Williamson <alwillia@redhat.com>" [full] # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" [full] # Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22 * remotes/awilliam/tags/vfio-fixes-20190702.0: vfio/pci: Trace vfio_set_irq_signaling() failure in vfio_msix_vector_release() vfio-common.h: Remove inaccurate comment Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-04Merge remote-tracking branch ↵Peter Maydell7-119/+220
'remotes/palmer/tags/riscv-for-master-4.1-sf1-v3' into staging RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 This pull request contains a handful of patches that I'd like to target for the 4.1 soft freeze. There are a handful of new features: * Support for the 1.11.0, the latest privileged specification. * Support for reading and writing the PRCI registers. * Better control over the ISA of the target machine. * Support for the cpu-topology device tree node. Additionally, there are a handful of bug fixes including: * Load reservations are now broken by both store conditional and by scheduling, which fixes issues with parallel applications. * Various fixes to the PMP implementation. * Fixes to the 32-bit linux-user syscall ABI. * Various fixes for instruction decodeing. * A fix to the PCI device tree "bus-range" property. This boots 32-bit and 64-bit OpenEmbedded. Changes since v2 [riscv-for-master-4.1-sf1-v2]: * Dropped OpenSBI. Changes since v1 [riscv-for-master-4.1-sf1]: * Contains a fix to the sifive_u OpenSBI integration. # gpg: Signature made Wed 03 Jul 2019 09:39:09 BST # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.1-sf1-v3: (32 commits) hw/riscv: Extend the kernel loading support hw/riscv: Add support for loading a firmware hw/riscv: Split out the boot functions riscv: sifive_u: Update the plic hart config to support multicore riscv: sifive_u: Do not create hard-coded phandles in DT disas/riscv: Fix `rdinstreth` constraint disas/riscv: Disassemble reserved compressed encodings as illegal riscv: virt: Add cpu-topology DT node. RISC-V: Update syscall list for 32-bit support. RISC-V: Clear load reservations on context switch and SC RISC-V: Add support for the Zicsr extension RISC-V: Add support for the Zifencei extension target/riscv: Add support for disabling/enabling Counters target/riscv: Remove user version information target/riscv: Require either I or E base extension qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 target/riscv: Set privledge spec 1.11.0 as default target/riscv: Add the mcountinhibit CSR target/riscv: Add the privledge spec version 1.11.0 target/riscv: Restructure deprecatd CPUs ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-04Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20190702' ↵Peter Maydell3-4/+36
into staging qemu-sparc queue # gpg: Signature made Tue 02 Jul 2019 23:14:13 BST # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-20190702: sunhme: ensure that RX descriptor ring overflow is indicated to client driver sunhme: fix return values from sunhme_receive() during receive packet processing sunhme: flush any queued packets when HME_MAC_RXCFG_ENABLE bit is raised sunhme: fix incorrect constant in sunhme_can_receive() sunhme: add trace event for logging PCI IRQ sun4m: set default display type to TCX Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-03Merge remote-tracking branch 'remotes/kraxel/tags/vga-20190703-pull-request' ↵Peter Maydell6-57/+22
into staging vga: virtio fixes, bitbang i2c asan fix, install ati vgabios. # gpg: Signature made Wed 03 Jul 2019 09:53:44 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20190703-pull-request: Add ati vgabios to INSTALL_BLOBS. hw/i2c/bitbang_i2c: Use in-place rather than malloc'd bitbang_i2c_interface struct virtio-gpu: check if the resource already exists in virtio_gpu_load() virtio-gpu: fix unmap in error path Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-03Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jul-02-2019' ↵Peter Maydell1-0/+30
into staging MIPS queue for July 2nd, 2019 # gpg: Signature made Tue 02 Jul 2019 17:09:29 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-jul-02-2019: target/mips: Correct helper for MSA FCLASS.<W|D> instructions target/mips: Unroll loops for MSA float max/min instructions target/mips: Correct comments in msa_helper.c target/mips: Correct comments in translate.c tcg/tests: target/mips: Correct MSA test compilation and execution order tcg/tests: target/mips: Amend MSA integer multiply tests tcg/tests: target/mips: Amend MSA fixed point multiply tests hw/mips: Express dependencies of the r4k platform with Kconfig hw/mips: Express dependencies of the Jazz machine with Kconfig hw/mips: Express dependencies of the MIPSsim machine with Kconfig hw/mips: Explicit the semi-hosting feature is always required tests/machine-none: Test recent MIPS cpus Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-03hw/i2c/bitbang_i2c: Use in-place rather than malloc'd bitbang_i2c_interface ↵Peter Maydell5-55/+15
struct Currently the bitbang_i2c_init() function allocates a bitbang_i2c_interface struct which it returns. This is unfortunate because it means that if the function is used from a DeviceState init method then the memory will be leaked by an "init then delete" cycle, as used by the qmp/hmp commands that list device properties. Since three out of four of the uses of this function are in device init methods, switch the function to do an in-place initialization of a struct that can be embedded in the device state struct of the caller. This fixes LeakSanitizer leak warnings that have appeared in the patchew configuration (which only tries to run the sanitizers for the x86_64-softmmu target) now that we use the bitbang-i2c code in an x86-64 config. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190702163844.20458-1-peter.maydell@linaro.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-07-03virtio-gpu: check if the resource already exists in virtio_gpu_load()Li Qiang1-0/+5
While loading virtio-gpu, the data can be malicious, we should check if the resource already exists. Signed-off-by: Li Qiang <liq3ea@163.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 20190628161358.10400-1-liq3ea@163.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-07-03virtio-gpu: fix unmap in error pathGerd Hoffmann1-2/+2
We land here in case not everything we've asked for could be mapped. So unmap only the bytes which have actually been mapped. Also we didn't access anything, so acces_len can be 0. Reported-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Message-id: 20190628072357.31782-1-kraxel@redhat.com
2019-07-03Merge remote-tracking branch ↵Peter Maydell9-6/+1107
'remotes/armbru/tags/pull-monitor-2019-07-02-v2' into staging Monitor patches for 2019-07-02 # gpg: Signature made Tue 02 Jul 2019 12:37:57 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-monitor-2019-07-02-v2: dump: Move HMP command handlers to dump/ MAINTAINERS: Add Windows dump to section "Dump" dump: Move the code to dump/ qapi: Split dump.json off misc.json qapi: Rename target.json to misc-target.json qapi: Split machine-target.json off target.json and misc.json hw/core: Collect HMP command handlers in hw/core/ hw/core: Collect QMP command handlers in hw/core/ hw/core: Move numa.c to hw/core/ qapi: Split machine.json off misc.json MAINTAINERS: Merge sections CPU, NUMA into Machine core qom: Move HMP command handlers to qom/ qom: Move QMP command handlers to qom/ qapi: Split qom.json and qdev.json off misc.json hmp: Move hmp.h to include/monitor/ Makefile: Don't add monitor/ twice to common-obj-y MAINTAINERS: Make section "QOM" cover qdev as well MAINTAINERS: new maintainers for QOM Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02sunhme: ensure that RX descriptor ring overflow is indicated to client driverMark Cave-Ayland2-0/+10
On very busy networks connected via a tap interface, it is possible to overflow the RX descriptor ring in the time between the client driver enabling the RX MAC and finishing writing the final configuration to the NIC registers. Ensure that we detect this condition and update the status register accordingly to indicate an overflow has occurred (and the incoming packet dropped) in order to prevent the client driver becoming confused. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2019-07-02sunhme: fix return values from sunhme_receive() during receive packet processingMark Cave-Ayland1-3/+3
The current return values in sunhme_receive() when processing incoming packets are inverted from what they should be. Make sure that we return 0 to indicate the packet was discarded (and polling is to be disabled) and -1 to indicate that the packet was discarded but polling for incoming data is to be continued. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2019-07-02sunhme: flush any queued packets when HME_MAC_RXCFG_ENABLE bit is raisedMark Cave-Ayland1-0/+10
Some client drivers use this bit to pause and resume the driver so make sure that queued packets are flushed when the MAC is disabled and then reactivated. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2019-07-02sunhme: fix incorrect constant in sunhme_can_receive()Mark Cave-Ayland1-1/+1
Due to a copy/paste error the wrong register was being checked in order to determine if the NIC is able to receive data. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2019-07-02sunhme: add trace event for logging PCI IRQMark Cave-Ayland2-0/+3
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2019-07-02sun4m: set default display type to TCXMark Cave-Ayland1-0/+9
Commit 6807874d55 "sun4m: obey -vga none" changed the sun4m machines so that they could be started without a framebuffer installed, but as no default display type was configured the machines would start in headless mode without an explict -vga option. Set the default display type for all sun4m machines to TCX so that they will start with a framebuffer if one is not specifically requested. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2019-07-02vfio/pci: Trace vfio_set_irq_signaling() failure in vfio_msix_vector_release()Eric Auger1-2/+5
Report an error in case we fail to set a trigger action on any VFIO_PCI_MSIX_IRQ_INDEX subindex. This might be useful in debugging a device that is not working properly. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reported-by: Coverity (CID 1402196) Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2019-07-02Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.1-20190702' ↵Peter Maydell15-255/+400
into staging ppc patch queue 2019-07-2 Here's my next pull request for qemu-4.1. I'm not sure if this will squeak in just before the soft freeze, or just after. I don't think it really matters - most of this is bugfixes anyway. There's some cleanups which aren't stictly bugfixes, but which I think are safe enough improvements to go in the soft freeze. There's no true feature work. Unfortunately, I wasn't able to complete a few of my standard battery of pre-pull tests, due to some failures that appear to also be in master. I'm hoping that hasn't missed anything important in here. Highlights are: * A number of fixe and cleanups for the XIVE implementation * Cleanups to the XICS interrupt controller to fit better with the new XIVE code * Numerous fixes and improvements to TCG handling of ppc vector instructions * Remove a number of unnnecessary #ifdef CONFIG_KVM guards * Fix some errors in the PCI hotplug paths * Assorted other fixes # gpg: Signature made Tue 02 Jul 2019 07:07:15 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-4.1-20190702: (49 commits) spapr/xive: Add proper rollback to kvmppc_xive_connect() ppc/xive: Fix TM_PULL_POOL_CTX special operation ppc/pnv: Rework cache watch model of PnvXIVE ppc/xive: Make the PIPR register readonly ppc/xive: Force the Physical CAM line value to group mode spapr/xive: simplify spapr_irq_init_device() to remove the emulated init spapr/xive: rework the mapping the KVM memory regions spapr_pci: Unregister listeners before destroying the IOMMU address space target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at translation time target/ppc: introduce GEN_VSX_HELPER_R2_AB macro to fpu_helper.c target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.c target/ppc: introduce GEN_VSX_HELPER_R3 macro to fpu_helper.c target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c target/ppc: introduce GEN_VSX_HELPER_X2_AB macro to fpu_helper.c target/ppc: introduce GEN_VSX_HELPER_X2 macro to fpu_helper.c target/ppc: introduce separate generator and helper for xscvqpdp target/ppc: introduce GEN_VSX_HELPER_X3 macro to fpu_helper.c target/ppc: introduce separate VSX_CMP macro for xvcmp* instructions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02Merge remote-tracking branch ↵Peter Maydell3-236/+492
'remotes/philmd-gitlab/tags/pflash-next-20190701' into staging Implement the following AMD command-set parallel flash functionality: - nonuniform sector sizes; - erase suspend/resume commands; and - multi-sector erase. # gpg: Signature made Tue 02 Jul 2019 01:54:33 BST # gpg: using RSA key E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/pflash-next-20190701: (27 commits) hw/block/pflash_cfi02: Reduce I/O accesses to 16-bit hw/block/pflash_cfi02: Document commands hw/block/pflash_cfi02: Use chip erase time specified in the CFI table hw/block/pflash_cfi02: Implement erase suspend/resume hw/block/pflash_cfi02: Implement multi-sector erase hw/block/pflash_cfi02: Fix reset command not ignored during erase hw/block/pflash_cfi02: Fix CFI in autoselect mode hw/block/pflash_cfi02: Split if() condition hw/block/pflash_cfi02: Extract pflash_regions_count() hw/block/pflash_cfi02: Implement nonuniform sector sizes hw/block/pflash_cfi02: Document 'Page Mode' operations are not supported hw/block/pflash_cfi02: Hold the PRI table offset in a variable hw/block/pflash_cfi02: Document the current CFI values hw/block/pflash_cfi02: Remove pointless local variable tests/pflash-cfi02: Refactor to support testing multiple configurations hw/block/pflash_cfi02: Fix command address comparison hw/block/pflash_cfi02: Unify the MemoryRegionOps hw/block/pflash_cfi02: Extract the pflash_data_read() function hw/block/pflash_cfi02: Use the ldst API in pflash_read() hw/block/pflash_cfi02: Use the ldst API in pflash_write() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into ↵Peter Maydell2-4/+2
staging # gpg: Signature made Tue 02 Jul 2019 03:21:54 BST # gpg: using RSA key EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * remotes/jasowang/tags/net-pull-request: migration/colo.c: Add missed filter notify for Xen COLO. COLO-compare: Add colo-compare remote notify support COLO-compare: Make the compare_chr_send() can send notification message. COLO-compare: Add remote notification chardev handler frame COLO-compare: Add new parameter to communicate with remote colo-frame net/announce: Expand test for stopping self announce net/announce: Add HMP optional ID net/announce: Add optional ID net/announce: Add HMP optional interface list net/announce: Allow optional list of interfaces net: remove unused get_str_sep() function net: use g_strsplit() for parsing host address and port net: avoid using variable length array in net_client_init() net: fix assertion failure when ipv6-prefixlen is not a number ftgmac100: do not link to netdev qemu-bridge-helper: Document known shortcomings MAINTAINERS: Add qemu-bridge-helper.c to "Network device backends" Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02hw/mips: Express dependencies of the r4k platform with KconfigPhilippe Mathieu-Daudé1-0/+10
This platform use standard PC devices connected to an ISA bus. Networking is provided by a ne2000 chipset. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190701112612.14758-5-philmd@redhat.com>
2019-07-02hw/mips: Express dependencies of the Jazz machine with KconfigPhilippe Mathieu-Daudé1-0/+17
The Jazz use the RC4030 Asic to provide an EISA bus and DMA/IRQ. The framebuffer display is managed by a G364, the network card is a Sonic DP83932. A QLogic ESP216 provides a SCSI bus. None, for the both machine variants (PICA-61 and Magnum 4000), the DP83932 chipset is soldered on the board, and is MMIO-mapped (selected via Chip Select). Therefore we have to enforce the 'select' Kconfig rule (we can not use the 'imply' rule helpful when devices are connected on a bus). Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190701112612.14758-4-philmd@redhat.com>
2019-07-02hw/mips: Express dependencies of the MIPSsim machine with KconfigPhilippe Mathieu-Daudé1-0/+3
The MIPSsim machine only emulates an 8250 UART and a simple network controller, connected via an ISA bus. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190701112612.14758-3-philmd@redhat.com>
2019-07-02Merge remote-tracking branch ↵Peter Maydell20-162/+1596
'remotes/pmaydell/tags/pull-target-arm-20190701' into staging target-arm queue: * hw/arm/boot: fix direct kernel boot with initrd * hw/arm/msf2-som: Exit when the cpu is not the expected one * i.mx7: fix bugs in PCI controller needed to boot recent kernels * aspeed: add RTC device * aspeed: fix some timer device bugs * aspeed: add swift-bmc board * aspeed: vic: Add support for legacy register interface * aspeed: add aspeed-xdma device * Add new sbsa-ref board for aarch64 * target/arm: code refactoring in preparation for support of compilation with TCG disabled # gpg: Signature made Mon 01 Jul 2019 17:38:10 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190701: (46 commits) target/arm: Declare some M-profile functions publicly target/arm: Declare arm_log_exception() function publicly target/arm: Restrict PSCI to TCG target/arm/vfp_helper: Restrict the SoftFloat use to TCG target/arm/vfp_helper: Extract vfp_set_fpscr_from_host() target/arm/vfp_helper: Extract vfp_set_fpscr_to_host() target/arm/vfp_helper: Move code around target/arm: Move TLB related routines to tlb_helper.c target/arm: Declare get_phys_addr() function publicly target/arm: Move CPU state dumping routines to cpu.c target/arm: Move the DC ZVA helper into op_helper target/arm: Fix coding style issues target/arm: Fix multiline comment syntax target/arm/helper: Remove unused include target/arm: Add copyright boilerplate target/arm: Makefile cleanup (softmmu) target/arm: Makefile cleanup (KVM) target/arm: Makefile cleanup (ARM) target/arm: Makefile cleanup (Aarch64) hw/arm: Add arm SBSA reference machine, devices part ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02qapi: Rename target.json to misc-target.jsonMarkus Armbruster3-4/+4
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-14-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2019-07-02hw/core: Collect HMP command handlers in hw/core/Markus Armbruster2-0/+165
Move the HMP handlers related to qapi/machine.json to hw/core/machine-hmp-cmds.c, where they are covered by MAINTAINERS section "Machine core", just like qapi/machine.json. Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Cc: "Dr. David Alan Gilbert" <dgilbert@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-12-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-07-02hw/core: Collect QMP command handlers in hw/core/Markus Armbruster3-62/+329
The handlers for qapi/machine.json's QMP commands are spread over cpus.c, hw/core/numa.c, monitor/misc.c, monitor/qmp-cmds.c, and vl.c. Move them all to new hw/core/machine-qmp-cmds.c, where they are covered by MAINTAINERS section "Machine core", just like qapi/machine.json. Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-11-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2019-07-02hw/core: Move numa.c to hw/core/Markus Armbruster2-0/+669
Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-10-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2019-07-02Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190701' into stagingPeter Maydell3-43/+166
- cleanup/refactoring in the cpu feature code - fix for a tcg test case - halt/clear support for vfio-ccw, and use a new helper # gpg: Signature made Mon 01 Jul 2019 12:08:41 BST # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20190701: s390x: add cpu feature/model files to KVM section vfio-ccw: support async command subregion vfio-ccw: use vfio_set_irq_signaling s390x/cpumodel: Prepend KDSA features with "KDSA" s390x/cpumodel: Rework CPU feature definition tests/tcg/s390x: Fix alignment of csst parameter list Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02qapi: Split qom.json and qdev.json off misc.jsonMarkus Armbruster2-2/+2
Move commands object-add, object-del, qom-get, qom-list, qom-list-properties, qom-list-types, and qom-set with their types from misc.json to new qom.json. Move commands device-list-properties, device_add, device-del, and event DEVICE_DELETED from misc.json to new qdev.json. Add both new files to MAINTAINERS section QOM. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Daniel P. Berrange" <berrange@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-5-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> [Straightforwardly updated for "MAINTAINERS: Make section "QOM" cover qdev as well"]
2019-07-02net/announce: Add optional IDDr. David Alan Gilbert1-2/+2
Previously there was a single instance of the timer used by monitor triggered announces, that's OK, but when combined with the previous change that lets you have announces for subsets of interfaces it's a bit restrictive if you want to do different things to different interfaces. Add an 'id' field to the announce, and maintain a list of the timers based on id. This allows you to for example: a) Start an announce going on interface eth0 for a long time b) Start an announce going on interface eth1 for a long time c) Kill the announce on eth0 while leaving eth1 going. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2019-07-02ftgmac100: do not link to netdevCédric Le Goater1-2/+0
qdev_set_nic_properties() is already used in the Aspeed SoC level to bind the ftgmac100 device to the netdev. This is fixing support for multiple net devices. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2019-07-02hw/block/pflash_cfi02: Reduce I/O accesses to 16-bitPhilippe Mathieu-Daudé1-4/+1
Parallel NOR flashes are limited to 16-bit bus accesses. Remove the 32-bit dead code. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190627202719.17739-29-philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Document commandsPhilippe Mathieu-Daudé1-21/+19
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190627202719.17739-28-philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Use chip erase time specified in the CFI tableStephen Checkoway1-2/+2
When erasing the chip, use the typical time specified in the CFI table rather than arbitrarily selecting 5 seconds. Since the currently unconfigurable value set in the table is 12, this means a chip erase takes 4096 ms so this isn't a big change in behavior. Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-11-stephen.checkoway@oberlin.edu> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Implement erase suspend/resumeStephen Checkoway1-14/+140
During a sector erase (but not a chip erase), the embeded erase program can be suspended. Once suspended, the sectors not selected for erasure may be read and programmed. Autoselect mode is allowed during erase suspend mode. Presumably, CFI queries are similarly allowed so this commit allows them as well. Since guest firmware can use status bits DQ7, DQ6, DQ3, and DQ2 to determine the current state of sector erasure, these bits are properly implemented. Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-10-stephen.checkoway@oberlin.edu> Acked-by: Thomas Huth <thuth@redhat.com> Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> [PMD: Rebased] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Implement multi-sector eraseStephen Checkoway1-18/+76
After two unlock cycles and a sector erase command, the AMD flash chips start a 50 us erase time out. Any additional sector erase commands add a sector to be erased and restart the 50 us timeout. During the timeout, status bit DQ3 is cleared. After the time out, DQ3 is asserted during erasure. Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-9-stephen.checkoway@oberlin.edu> Acked-by: Thomas Huth <thuth@redhat.com> Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com> [PMD: Rebased] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Fix reset command not ignored during eraseStephen Checkoway1-1/+2
When the flash device is performing a chip erase, all commands are ignored. When it is performing a sector erase, only the erase suspend command is valid, which is currently not supported. In particular, the reset command should not cause the device to reset to read array mode while programming is on going. Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-8-stephen.checkoway@oberlin.edu> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Fix CFI in autoselect modeStephen Checkoway1-4/+18
After a flash device enters CFI mode from autoselect mode, the reset command returns the device to autoselect mode. An additional reset command is necessary to return to read array mode. Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-7-stephen.checkoway@oberlin.edu> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Split if() conditionPhilippe Mathieu-Daudé1-2/+4
Split the if() condition check and arrange the indentation to ease the review of the next patches. No logical change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190627202719.17739-21-philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Extract pflash_regions_count()Philippe Mathieu-Daudé1-2/+6
Extract the pflash_regions_count() function, the code will be easier to review. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190627202719.17739-20-philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Implement nonuniform sector sizesStephen Checkoway1-27/+114
Some flash chips support sectors of different sizes. For example, the AMD AM29LV160DT has 31 64 kB sectors, one 32 kB sector, two 8 kB sectors, and a 16 kB sector, in that order. The AM29LV160DB has those in the reverse order. The `num-blocks` and `sector-length` properties work exactly as they did before: a flash device with uniform sector lengths. To get non-uniform sector lengths for up to four regions, the following properties may be set - region 0. `num-blocks0` and `sector-length0`; - region 1. `num-blocks1` and `sector-length1`; - region 2. `num-blocks2` and `sector-length2`; and - region 3. `num-blocks3` and `sector-length3`. If the uniform and nonuniform properties are set, then both must specify a flash device with the same total size. It would be better to disallow both being set, or make `num-blocks0` and `sector-length0` alias `num-blocks` and `sector-length`, but that would make testing currently impossible. Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-6-stephen.checkoway@oberlin.edu> Acked-by: Thomas Huth <thuth@redhat.com> Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> [PMD: Rebased, add assert() on pri_offset] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Document 'Page Mode' operations are not supportedPhilippe Mathieu-Daudé1-1/+3
The 'page mode' feature entry was implicitly set as zero (not supported). Document it exists, so we won't discard it if we squeeze the CFI table. Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-6-stephen.checkoway@oberlin.edu> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> [PMD: Extracted from bigger patch] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Hold the PRI table offset in a variablePhilippe Mathieu-Daudé1-14/+17
Manufacturers are allowed to move the PRI table, this is why the offset is queryable via fixed offsets 0x15/0x16. Add a variable to hold the offset, so it will be easier to later move the PRI table. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190627202719.17739-17-philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Document the current CFI valuesPhilippe Mathieu-Daudé1-1/+10
Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-6-stephen.checkoway@oberlin.edu> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> [PMD: Extracted from bigger patch] Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Remove pointless local variablePhilippe Mathieu-Daudé1-8/+6
We can directly use pfl->total_len, remove the local 'chip_len' variable. Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-6-stephen.checkoway@oberlin.edu> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> [PMD: Extracted from bigger patch] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Fix command address comparisonStephen Checkoway1-1/+7
Most AMD commands only examine 11 bits of the address. This masks the addresses used in the comparison to 11 bits. The exceptions are word or sector addresses which use offset directly rather than the shifted offset, boff. Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-4-stephen.checkoway@oberlin.edu> Acked-by: Thomas Huth <thuth@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-02hw/block/pflash_cfi02: Unify the MemoryRegionOpsPhilippe Mathieu-Daudé1-45/+15
The pflash_read()/pflash_write() can check the device endianess via the pfl->be variable, so remove the 'int be' argument. Since the big/little MemoryRegionOps are now identical, it is pointless to declare them both. Unify them. Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-3-stephen.checkoway@oberlin.edu> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> [PMD: Extracted from bigger patch to ease review] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
generated by cgit v1.1 at 2024-10-18 13:20:00 +0000