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2019-02-01Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell3-20/+58
Block layer patches: - vmdk: Support for blockdev-create - block: Apply auto-read-only for ro-whitelist drivers - virtio-scsi: Fixes related to attaching/detaching iothreads - scsi-disk: Fixed erroneously detected multipath setup with multiple disks created with node-names. Added device_id property. - block: Fix hangs in synchronous APIs with iothreads - block: Fix invalidate_cache error path for parent activation - block-backend, mirror, qcow2, vpc, vdi, qemu-iotests: Minor fixes and code improvements # gpg: Signature made Fri 01 Feb 2019 15:23:10 GMT # gpg: using RSA key 7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (27 commits) scsi-disk: Add device_id property scsi-disk: Don't use empty string as device id qtest.py: Wait for the result of qtest commands block: Fix invalidate_cache error path for parent activation iotests/236: fix transaction kwarg order iotests: Filter second BLOCK_JOB_ERROR from 229 virtio-scsi: Forbid devices with different iothreads sharing a blockdev scsi-disk: Acquire the AioContext in scsi_*_realize() virtio-scsi: Move BlockBackend back to the main AioContext on unplug block: Eliminate the S_1KiB, S_2KiB, ... macros block: Remove blk_attach_dev_legacy() / legacy_dev code block: Apply auto-read-only for ro-whitelist drivers uuid: Make qemu_uuid_bswap() take and return a QemuUUID block/vdi: Don't take address of fields in packed structs block/vpc: Don't take address of fields in packed structs vmdk: Reject excess extents in blockdev-create iotests: Add VMDK tests for blockdev-create iotests: Filter cid numbers in VMDK extent info vmdk: Implement .bdrv_co_create callback vmdk: Refactor vmdk_create_extent ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01Merge remote-tracking branch ↵Peter Maydell15-810/+1935
'remotes/pmaydell/tags/pull-target-arm-20190201' into staging target-arm queue: * New machine mps2-an521 -- this is a model of the AN521 FPGA image for the MPS2 devboard * Fix various places where we failed to UNDEF invalid A64 instructions * Don't UNDEF a valid FCMLA on 32-bit inputs * Fix some bugs in the newly-added PAuth implementation * microbit: Implement NVMC non-volatile memory controller # gpg: Signature made Fri 01 Feb 2019 16:06:03 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190201: (47 commits) tests/microbit-test: Add tests for nRF51 NVMC arm: Instantiate NRF51 special NVM's and NVMC hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories target/arm: fix decoding of B{,L}RA{A,B} target/arm: fix AArch64 virtual address space size linux-user: Initialize aarch64 pac keys aarch64-linux-user: Enable HWCAP bits for PAuth aarch64-linux-user: Update HWCAP bits from linux 5.0-rc1 target/arm: Always enable pac keys for user-only arm: Clarify the logic of set_pc() target/arm: Enable API, APK bits in SCR, HCR target/arm: Add a timer to predict PMU counter overflow target/arm: Send interrupts on PMU counter overflow target/arm/translate-a64: Fix mishandling of size in FCMLA decode target/arm/translate-a64: Fix FCMLA decoding error exec.c: Don't reallocate IOMMUNotifiers that are in use target/arm/translate-a64: Don't underdecode SDOT and UDOT target/arm/translate-a64: Don't underdecode FP insns target/arm/translate-a64: Don't underdecode add/sub extended register target/arm/translate-a64: Don't underdecode SIMD ld/st single ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01arm: Instantiate NRF51 special NVM's and NVMCSteffen Görtz1-12/+29
Instantiates UICR, FICR, FLASH and NVMC in nRF51 SOC. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190201023357.22596-3-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01hw/nvram/nrf51_nvm: Add nRF51 non-volatile memoriesSteffen Görtz2-0/+389
The nRF51 contains three regions of non-volatile memory (NVM): - CODE (R/W): contains code - FICR (R): Factory information like code size, chip id etc. - UICR (R/W): Changeable configuration data. Lock bits, Code protection configuration, Bootloader address, Nordic SoftRadio configuration, Firmware configuration. Read and write access to the memories is managed by the Non-volatile memory controller. Memory schema: [ CPU ] -+- [ NVM, either FICR, UICR or CODE ] | | \- [ NVMC ] Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Tested-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190201023357.22596-2-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01arm: Clarify the logic of set_pc()Julia Suvorova1-4/+0
Until now, the set_pc logic was unclear, which raised questions about whether it should be used directly, applying a value to PC or adding additional checks, for example, set the Thumb bit in Arm cpu. Let's set the set_pc logic for “Configure the PC, as was done in the ELF file” and implement synchronize_with_tb hook for preserving PC to cpu_tb_exec. Signed-off-by: Julia Suvorova <jusual@mail.ru> Acked-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190129121817.7109-1-jusual@mail.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01hw/arm/mps2-tz: Add mps2-an521 modelPeter Maydell1-2/+36
Add a model of the MPS2 FPGA image described in Application Note AN521. This is identical to the AN505 image, except that it uses the SSE-200 rather than the IoTKit and so has two Cortex-M33 CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-24-peter.maydell@linaro.org
2019-02-01hw/arm/mps2-tz: Add IRQ infrastructure to support SSE-200Peter Maydell1-20/+59
In preparation for adding support for the AN521 MPS2 image, we need to handle wiring up the MPS2 device interrupt lines to both CPUs in the SSE-200, rather than just the one that the IoTKit has. Abstract out a "connect to the IoTKit interrupt line" function and make it connect to a splitter which feeds both sets of inputs for the SSE-200 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-23-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add SSE-200 modelPeter Maydell1-0/+12
Add a model of the SSE-200, now we have put in all the code that lets us make it different from the IoTKit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-22-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add CPU_IDENTITY block to SSE-200Peter Maydell1-0/+28
Instantiate a copy of the CPU_IDENTITY register block for each CPU in an SSE-200. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-21-peter.maydell@linaro.org
2019-02-01hw/misc/armsse-cpuid: Implement SSE-200 CPU_IDENTITY register blockPeter Maydell3-0/+139
The SSE-200 has a CPU_IDENTITY register block, which is a set of read-only registers. As well as the usual PID/CID registers, there is a single CPUID register which indicates whether the CPU is CPU 0 or CPU 1. Implement a model of this register block. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-20-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add unimplemented-device stub for CPU local control registersPeter Maydell1-0/+31
The SSE-200 has a "CPU local security control" register bank; add an unimplemented-device stub for it. (The register bank has only one interesting register, which allows the guest to lock down changes to various CPU registers so they cannot be modified further. We don't support that in our Cortex-M33 model anyway.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-19-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add unimplemented-device stub for cache control registersPeter Maydell1-1/+38
The SSE-200 gives each CPU a register bank to use to control its L1 instruction cache. Put in an unimplemented-device stub for this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-18-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add unimplemented-device stubs for PPUsPeter Maydell1-0/+58
Add unimplemented-device stubs for the various Power Policy Unit devices that the SSE-200 has. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-17-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Add unimplemented-device stubs for MHUsPeter Maydell1-0/+41
The SSE-200 has two Message Handling Units (MHUs), which sit behind the APB PPC0. Wire up some unimplemented-device stubs for these, since we don't yet implement a real model of this device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-16-peter.maydell@linaro.org
2019-02-01iotkit-sysinfo: Make SYS_VERSION and SYS_CONFIG configurablePeter Maydell2-2/+64
The SYS_VERSION and SYS_CONFIG register values differ between the IoTKit and SSE-200. Make them configurable via QOM properties rather than hard-coded, and set them appropriately in the ARMSSE code that instantiates the IOTKIT_SYSINFO device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-15-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Put each CPU in its own cluster objectPeter Maydell1-3/+28
Create a cluster object to hold each CPU in the SSE. They are logically distinct and may be configured differently (for instance one may not have an FPU where the other does). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-14-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Give each CPU its own view of memoryPeter Maydell1-2/+20
Give each CPU its own container memory region. This is necessary for two reasons: * some devices are instantiated one per CPU and the CPU sees only its own device * since a memory region can only be put into one container, we must give each armv7m object a different MemoryRegion as its 'memory' property, or a dual-CPU configuration will assert on realize when the second armv7m object tries to put the MR into a container when it is already in the first armv7m object's container Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-13-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Support dual-CPU configurationPeter Maydell1-42/+164
The SSE-200 has two Cortex-M33 CPUs. These see the same view of memory, with the exception of the "private CPU region" which has per-CPU devices. Internal device interrupts for SSE-200 devices are mostly wired up to both CPUs, with the exception of a few per-CPU devices. External GPIO inputs on the SSE-200 device are provided for the second CPU's interrupts above 32, as is already the case for the first CPU. Refactor the code to support creation of multiple CPUs. For the moment we leave all CPUs with the same view of memory: this will not work in the multiple-CPU case, but we will fix this in the following commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-12-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Make SRAM bank size configurablePeter Maydell1-2/+16
For the IoTKit the SRAM bank size is always 32K (15 bits); for the SSE-200 this is a configurable parameter, which defaults to 32K but can be changed when it is built into a particular SoC. For instance the Musca-B1 board sets it to 128K (17 bits). Make the bank size a QOM property. We follow the SSE-200 hardware in naming the parameter SRAM_ADDR_WIDTH, which specifies the number of address bits of a single SRAM bank. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-11-peter.maydell@linaro.org
2019-02-01hw/arm/armsse: Make number of SRAM banks parameterisedPeter Maydell1-29/+49
The SSE-200 has four banks of SRAM, each with its own Memory Protection Controller, where the IoTKit has only one. Make the number of SRAM banks a field in ARMSSEInfo. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-10-peter.maydell@linaro.org
2019-02-01hw/misc/iotkit-secctl: Support 4 internal MPCsPeter Maydell2-5/+6
The SSE-200 has 4 banks of SRAM, each with its own internal Memory Protection Controller. The interrupt status for these extra MPCs appears in the same security controller SECMPCINTSTATUS register as the MPC for the IoTKit's single SRAM bank. Enhance the iotkit-secctl device to allow 4 MPCs. (If the particular IoTKit/SSE variant in use does not have all 4 MPCs then the unused inputs will simply result in the SECMPCINTSTATUS bits being zero as required.) The hardcoded constant "1"s in armsse.c indicate the actual number of SRAM MPCs the IoTKit has, and will be replaced in the following commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-9-peter.maydell@linaro.org
2019-02-01hw/arm/iotkit: Rename files to hw/arm/armsse.[ch]Peter Maydell3-3/+3
Rename the files that used to be iotkit.[ch] to armsse.[ch] to reflect the fact they new cover multiple Arm subsystems for embedded. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-8-peter.maydell@linaro.org
2019-02-01hw/arm/iotkit: Rename 'iotkit' local variables and functionsPeter Maydell1-34/+34
Rename various internal uses of 'iotkit' in hw/arm/iotkit.c to 'armsse', for consistency. The remaining occurences are: * related to the devices TYPE_IOTKIT_SYSCTL, TYPE_IOTKIT_SYSINFO, etc, which this refactor is not touching * references that apply specifically to the IoTKit (like the lack of a private CPU region) * the vmstate, which keeps its old "iotkit" name for migration compatibility reasons Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-7-peter.maydell@linaro.org
2019-02-01hw/arm/iotkit: Refactor into abstract base class and subclassPeter Maydell1-5/+29
The Arm SSE-200 Subsystem for Embedded is a revised and extended version of the older IoTKit SoC. Prepare for adding a model of it by refactoring the IoTKit code into an abstract base class which contains the functionality, driven by a class data block specific to each subclass. (This is the same approach used by the existing bcm283x SoC family implementation.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-6-peter.maydell@linaro.org
2019-02-01hw/arm/iotkit: Rename IoTKit to ARMSSEPeter Maydell2-30/+31
The Arm IoTKit was effectively the forerunner of a series of subsystems for embedded SoCs, named the SSE-050, SSE-100 and SSE-200: https://developer.arm.com/products/system-design/subsystems These are generally quite similar, though later iterations have extra devices that earlier ones do not. We want to add a model of the SSE-200, which means refactoring the IoTKit code into an abstract base class and subclasses (using the same design that the bcm283x SoC and Aspeed SoC family implementations do). As a first step, rename the IoTKit struct and QOM macros to ARMSSE, which is what we're going to name the base class. We temporarily retain TYPE_IOTKIT to avoid changing the code that instantiates a TYPE_IOTKIT device here and then changing it back again when it is re-introduced as a subclass. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-5-peter.maydell@linaro.org
2019-02-01armv7m: Pass through start-powered-off CPU propertyPeter Maydell1-0/+10
Expose "start-powered-off" as a property of the ARMv7M container, which we just pass through to the CPU object in the same way that we do for "init-svtor" and "idau". (We want this for the SSE-200, which powers up only the first CPU at reset and leaves the second powered down.) As with the other CPU properties here, we can't just use alias properties, because the CPU QOM object is not created until armv7m realize time. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-4-peter.maydell@linaro.org
2019-02-01armv7m: Make cpu object a child of the armv7m containerPeter Maydell1-1/+6
Rather than just creating the CPUs with object_new, make them child objects of the armv7m container. This will allow the cluster code to find the CPUs if an armv7m object is made a child of a cluster object. object_new_with_props() will do the parenting for us. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-3-peter.maydell@linaro.org
2019-02-01armv7m: Don't assume the NVIC's CPU is CPU 0Peter Maydell2-4/+5
Currently the ARMv7M NVIC object's realize method assumes that the CPU the NVIC is attached to is CPU 0, because it thinks there can only ever be one CPU in the system. To allow a dual-Cortex-M33 setup we need to remove this assumption; instead the armv7m wrapper object tells the NVIC its CPU, in the same way that it already tells the CPU what the NVIC is. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-2-peter.maydell@linaro.org
2019-02-01hw/arm/nrf51_soc: set object owner in memory_region_init_ramkumar sourav1-1/+2
set object owner in memory_region_init_ram() instead of NULL. Signed-off-by: kumar sourav <sourav.jb1988@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190125155630.17430-1-sourav.jb1988@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01Merge remote-tracking branch 'remotes/kraxel/tags/ui-20190201-pull-request' ↵Peter Maydell4-67/+54
into staging ui: fix build with SDL disabled, drop SDL1 support. # gpg: Signature made Fri 01 Feb 2019 12:30:47 GMT # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20190201-pull-request: ui: remove support for SDL1.2 in favour of SDL2 hw/display/milkymist-tmu2: Move inlined code from header to source hw/display/milkymist-tmu2: Explicit the dependency to both X11 / OpenGL configure: LM32 Milkymist Texture Mapping Unit (tmu2) also depends of X11 hw/display: Move Milkymist specific hardware out of common-obj list Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01scsi-disk: Add device_id propertyKevin Wolf1-8/+16
The new device_id property specifies which value to use for the vendor specific designator in the Device Identification VPD page. In particular, this is necessary for libvirt to maintain guest ABI compatibility when no serial number is given and a VM is switched from -drive (where the BlockBackend name is used) to -blockdev (where the vendor specific designator is left out by default). Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2019-02-01scsi-disk: Don't use empty string as device idKevin Wolf1-6/+8
scsi-disk includes in the Device Identification VPD page, depending on configuration amongst others, a vendor specific designator that consists either of the serial number if given or the BlockBackend name (which is a host detail that better shouldn't have been leaked to the guest, but now we have to maintain it for compatibility). With anonymous BlockBackends, i.e. scsi-disk devices constructed with drive=<node-name>, and no serial number explicitly specified, this ends up as an empty string. If this happens to more than one disk, we have accidentally signalled to the OS that this is a multipath setup, which is obviously not what was intended. Instead of using an empty string for the vendor specific designator, simply leave out that designator, which makes Linux detect such setups as separate disks again. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-02-01virtio-scsi: Forbid devices with different iothreads sharing a blockdevAlberto Garcia1-0/+7
This patch forbids attaching a disk to a SCSI device if its using a different AioContext. Test case included. Signed-off-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2019-02-01scsi-disk: Acquire the AioContext in scsi_*_realize()Alberto Garcia1-3/+20
This fixes a crash when attaching two disks with the same blockdev to a SCSI device that is using iothreads. Test case included. Signed-off-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2019-02-01virtio-scsi: Move BlockBackend back to the main AioContext on unplugAlberto Garcia1-0/+6
This fixes a crash when attaching a disk to a SCSI device using iothreads, then detaching it and reattaching it again. Test case included. Signed-off-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2019-02-01uuid: Make qemu_uuid_bswap() take and return a QemuUUIDPeter Maydell1-4/+2
Currently qemu_uuid_bswap() takes a pointer to the QemuUUID to be byte-swapped. This means it can't be used when the UUID to be swapped is in a packed member of a struct. It's also out of line with the general bswap*() functions we provide in bswap.h, which take the value to be swapped and return it. Make qemu_uuid_bswap() take a QemuUUID and return the swapped version. This fixes some clang warnings about taking the address of a packed struct member in block/vdi.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2019-02-01hw/display/milkymist-tmu2: Move inlined code from header to sourcePhilippe Mathieu-Daudé3-63/+50
Move the complexity of milkymist_tmu2_create() into the source file. Doing so we avoid to include the X11/OpenGL headers in all LM32 devices, and we also avoid the duplicate declaration of glx_fbconfig_attr[] (it is already declared in hw/display/milkymist-tmu2.c). Since TYPE_MILKYMIST_TMU2 is now accessible, use it. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190130120005.23123-5-philmd@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-02-01hw/display/milkymist-tmu2: Explicit the dependency to both X11 / OpenGLPhilippe Mathieu-Daudé2-4/+4
The TMU device requires both X11 and OpenGL. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190130120005.23123-4-philmd@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-02-01hw/display: Move Milkymist specific hardware out of common-obj listPhilippe Mathieu-Daudé1-2/+2
The Milkymist specific hardware is only used by the LM32 target, it is pointless to compile those objects in other targets. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190130120005.23123-2-philmd@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-01-31Merge remote-tracking branch 'remotes/xanclic/tags/pull-block-2019-01-31' ↵Peter Maydell1-5/+10
into staging Block patches: - New debugging QMP command to explore block graphs - Converted DPRINTF()s to trace events - Fixed qemu-io's use of getopt() for systems with optreset - Minor NVMe emulation fixes - An iotest fix # gpg: Signature made Thu 31 Jan 2019 00:51:46 GMT # gpg: using RSA key F407DB0061D5CF40 # gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full] # Primary key fingerprint: 91BE B60A 30DB 3E88 57D1 1829 F407 DB00 61D5 CF40 * remotes/xanclic/tags/pull-block-2019-01-31: iotests: Allow 147 to be run concurrently iotests: Bind qemu-nbd to localhost in 147 iotests.py: Add qemu_nbd_pipe() nvme: use pci_dev directly in nvme_realize nvme: ensure the num_queues is not zero nvme: use TYPE_NVME instead of constant string qemu-io: Add generic function for reinitializing optind. block/sheepdog: Convert from DPRINTF() macro to trace events block/file-posix: Convert from DPRINTF() macro to trace events block/curl: Convert from DPRINTF() macro to trace events block/ssh: Convert from DPRINTF() macro to trace events scripts: add render_block_graph function for QEMUMachine qapi: add x-debug-query-block-graph Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-31Merge remote-tracking branch ↵Peter Maydell7-11/+6
'remotes/vivier2/tags/trivial-branch-pull-request' into staging - add device category (edu, i8042, sd memory card) - code clean-up - LGPL information clean-up - fix typo (acpi) # gpg: Signature made Wed 30 Jan 2019 13:21:50 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-pull-request: virtio-blk: remove duplicate definition of VirtIOBlock *s pointer hw/block: clean up stale xen_disk trace entries target/m68k: Fix LGPL information in the file headers target/s390x: Fix LGPL version in the file header comments tcg: Fix LGPL version number target/tricore: Fix LGPL version number target/openrisc: Fix LGPL version number COPYING.LIB: Synchronize the LGPL 2.1 with the version from gnu.org Don't talk about the LGPL if the file is licensed under the GPL hw: sd: set category of the sd memory card hw: input: set category of the i8042 device typo: apci->acpi hw: edu: set category of the edu device Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-31Merge remote-tracking branch 'remotes/kraxel/tags/usb-20190130-pull-request' ↵Peter Maydell10-88/+153
into staging usb: xhci: fix iso transfers. usb: mtp: break up writes, bugfixes. usb: fix lgpl info in headers. usb: hid: unique serials. # gpg: Signature made Wed 30 Jan 2019 07:33:21 GMT # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/usb-20190130-pull-request: usb-mtp: replace the homebrew write with qemu_write_full usb-mtp: breakup MTP write into smaller chunks usb-mtp: Reallocate buffer in multiples of MTP_WRITE_BUF_SZ usb: implement XHCI underrun/overrun events usb: XHCI shall not halt isochronous endpoints hw/usb: Fix LGPL information in the file headers usb: dev-mtp: close fd in usb_mtp_object_readdir() usb: assign unique serial numbers to hid devices Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-31Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' ↵Peter Maydell5-8/+14
into staging Pull request User-visible changes: * The new qemu-trace-stap script makes it convenient to collect traces without writing SystemTap scripts. See "man qemu-trace-stap" for details. # gpg: Signature made Wed 30 Jan 2019 03:17:57 GMT # gpg: using RSA key 9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/tracing-pull-request: trace: rerun tracetool after ./configure changes trace: improve runstate tracing trace: add ability to do simple printf logging via systemtap trace: forbid use of %m in trace event format strings trace: enforce that every trace-events file has a final newline display: ensure qxl log_buf is a nul terminated string Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-31nvme: use pci_dev directly in nvme_realizeLi Qiang1-4/+4
There is no need to make another reference. Signed-off-by: Li Qiang <liq3ea@163.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190120055558.32984-4-liq3ea@163.com Signed-off-by: Max Reitz <mreitz@redhat.com>
2019-01-31nvme: ensure the num_queues is not zeroLi Qiang1-0/+5
When it is zero, it causes segv. Using following command: "-drive file=//home/test/test1.img,if=none,id=id0 -device nvme,drive=id0,serial=test,num_queues=0" causes following Backtrack: Thread 4 "qemu-system-x86" received signal SIGSEGV, Segmentation fault. [Switching to Thread 0x7fffe9735700 (LWP 30952)] 0x0000555555a7a77c in nvme_start_ctrl (n=0x5555577473f0) at hw/block/nvme.c:825 825 if (unlikely(n->cq[0])) { (gdb) bt 0 0x0000555555a7a77c in nvme_start_ctrl (n=0x5555577473f0) at hw/block/nvme.c:825 1 0x0000555555a7af7f in nvme_write_bar (n=0x5555577473f0, offset=20, data=4587521, size=4) at hw/block/nvme.c:969 2 0x0000555555a7b81a in nvme_mmio_write (opaque=0x5555577473f0, addr=20, data=4587521, size=4) at hw/block/nvme.c:1163 3 0x0000555555869236 in memory_region_write_accessor (mr=0x555557747cd0, addr=20, value=0x7fffe97320f8, size=4, shift=0, mask=4294967295, attrs=...) at /home/test/qemu1/qemu/memory.c:502 4 0x0000555555869446 in access_with_adjusted_size (addr=20, value=0x7fffe97320f8, size=4, access_size_min=2, access_size_max=8, access_fn=0x55555586914d <memory_region_write_accessor>, mr=0x555557747cd0, attrs=...) at /home/test/qemu1/qemu/memory.c:568 5 0x000055555586c479 in memory_region_dispatch_write (mr=0x555557747cd0, addr=20, data=4587521, size=4, attrs=...) at /home/test/qemu1/qemu/memory.c:1499 6 0x00005555558030af in flatview_write_continue (fv=0x7fffe0061130, addr=4273930260, attrs=..., buf=0x7ffff7ff0028 "\001", len=4, addr1=20, l=4, mr=0x555557747cd0) at /home/test/qemu1/qemu/exec.c:3234 7 0x00005555558031f9 in flatview_write (fv=0x7fffe0061130, addr=4273930260, attrs=..., buf=0x7ffff7ff0028 "\001", len=4) at /home/test/qemu1/qemu/exec.c:3273 8 0x00005555558034ff in address_space_write ( ---Type <return> to continue, or q <return> to quit--- as=0x555556758480 <address_space_memory>, addr=4273930260, attrs=..., buf=0x7ffff7ff0028 "\001", len=4) at /home/test/qemu1/qemu/exec.c:3363 9 0x0000555555803550 in address_space_rw ( as=0x555556758480 <address_space_memory>, addr=4273930260, attrs=..., buf=0x7ffff7ff0028 "\001", len=4, is_write=true) at /home/test/qemu1/qemu/exec.c:3374 10 0x00005555558884a1 in kvm_cpu_exec (cpu=0x555556920e40) at /home/test/qemu1/qemu/accel/kvm/kvm-all.c:2031 11 0x000055555584cd9d in qemu_kvm_cpu_thread_fn (arg=0x555556920e40) at /home/test/qemu1/qemu/cpus.c:1281 12 0x0000555555dbaf6d in qemu_thread_start (args=0x5555569438a0) at util/qemu-thread-posix.c:502 13 0x00007ffff5dc86db in start_thread (arg=0x7fffe9735700) at pthread_create.c:463 14 0x00007ffff5af188f in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:95 Signed-off-by: Li Qiang <liq3ea@163.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190120055558.32984-3-liq3ea@163.com Signed-off-by: Max Reitz <mreitz@redhat.com>
2019-01-31nvme: use TYPE_NVME instead of constant stringLi Qiang1-1/+1
Signed-off-by: Li Qiang <liq3ea@163.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190120055558.32984-2-liq3ea@163.com Signed-off-by: Max Reitz <mreitz@redhat.com>
2019-01-30virtio-blk: remove duplicate definition of VirtIOBlock *s pointerStefano Garzarella1-2/+0
VirtIOBlock *s is already defined and initialized with req->dev on top of virtio_blk_handle_request(), so we can remove it from the code block of VIRTIO_BLK_T_GET_ID case. Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190130095231.42081-1-sgarzare@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-30hw/block: clean up stale xen_disk trace entriesPaul Durrant1-7/+0
This should have been removed then xen_disk.c was removed but I missed them. Fixes: 19f87870baa570bcd7e80e7657e030bf427f16be xen: remove the legacy 'xen_disk' backend Signed-off-by: Paul Durrant <paul.durrant@citrix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190122145132.12571-1-paul.durrant@citrix.com> [lv: s/stake/stale/ and add "Fixes" tag] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-30hw: sd: set category of the sd memory cardkumar sourav1-0/+1
Sets the category of the sd memory card as DEVICE_CATEGORY_STORAGE. Devices should be assigned to one of DEVICE_CATEGORY_XXXX. Signed-off-by: kumar sourav <sourav.jb1988@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190124162045.10474-1-sourav.jb1988@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-30hw: input: set category of the i8042 devicekumar sourav1-0/+1
Sets the category of i8042 device as DEVICE_CATEGORY_INPUT Devices should be assigned to one of DEVICE_CATEGORY_XXXX. Signed-off-by: kumar sourav <sourav.jb1988@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20190125151440.13794-1-sourav.jb1988@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
generated by cgit v1.1 at 2025-02-16 03:54:52 +0000