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2021-02-05accel/tcg: split TCG-only code from cpu_exec_realizefnClaudio Fontana1-1/+5
move away TCG-only code, make it compile only on TCG. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: moved the prototypes from hw/core/cpu.h to exec/cpu-all.h] Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-4-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05acpi: use constants as strncpy limitMichael S. Tsirkin3-6/+6
gcc is not smart enough to figure out length was validated before use as strncpy limit, resulting in this warning: inlined from ‘virt_set_oem_table_id’ at ../../hw/arm/virt.c:2197:5: /usr/include/aarch64-linux-gnu/bits/string_fortified.h:106:10: error: ‘__builtin_strncpy’ specified bound depends on the length of the source argument [-Werror=stringop-overflow=] Simplify things by using a constant limit instead. Fixes: 97fc5d507fca ("acpi: Permit OEM ID and OEM table ID fields to be changed") Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-05acpi: Permit OEM ID and OEM table ID fields to be changedMarian Postevca15-83/+326
Qemu's ACPI table generation sets the fields OEM ID and OEM table ID to "BOCHS " and "BXPCxxxx" where "xxxx" is replaced by the ACPI table name. Some games like Red Dead Redemption 2 seem to check the ACPI OEM ID and OEM table ID for the strings "BOCHS" and "BXPC" and if they are found, the game crashes(this may be an intentional detection mechanism to prevent playing the game in a virtualized environment). This patch allows you to override these default values. The feature can be used in this manner: qemu -machine oem-id=ABCDEF,oem-table-id=GHIJKLMN The oem-id string can be up to 6 bytes in size, and the oem-table-id string can be up to 8 bytes in size. If the string are smaller than their respective sizes they will be padded with space. If either of these parameters is not set, the current default values will be used for the one missing. Note that the the OEM Table ID field will not be extended with the name of the table, but will use either the default name or the user provided one. This does not affect the -acpitable option (for user-defined ACPI tables), which has precedence over -machine option. Signed-off-by: Marian Postevca <posteuca@mutex.one> Message-Id: <20210119003216.17637-3-posteuca@mutex.one> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-05vhost: Check for valid vdev in vhost_backend_handle_iotlb_msgEugenio Pérez1-0/+5
Not checking this can lead to invalid dev->vdev member access in vhost_device_iotlb_miss if backend issue an iotlb message in a bad timing, either maliciously or by a bug. Reproduced rebooting a guest with testpmd in txonly forward mode. #0 0x0000559ffff94394 in vhost_device_iotlb_miss ( dev=dev@entry=0x55a0012f6680, iova=10245279744, write=1) at ../hw/virtio/vhost.c:1013 #1 0x0000559ffff9ac31 in vhost_backend_handle_iotlb_msg ( imsg=0x7ffddcfd32c0, dev=0x55a0012f6680) at ../hw/virtio/vhost-backend.c:411 #2 vhost_backend_handle_iotlb_msg (dev=dev@entry=0x55a0012f6680, imsg=imsg@entry=0x7ffddcfd32c0) at ../hw/virtio/vhost-backend.c:404 #3 0x0000559fffeded7b in slave_read (opaque=0x55a0012f6680) at ../hw/virtio/vhost-user.c:1464 #4 0x000055a0000c541b in aio_dispatch_handler ( ctx=ctx@entry=0x55a0010a2120, node=0x55a0012d9e00) at ../util/aio-posix.c:329 Fixes: 020e571b8b ("vhost: rework IOTLB messaging") Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Message-Id: <20210129090728.831208-1-eperezma@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-05hw/virtio/virtio-balloon: Remove the "class" propertyThomas Huth1-10/+1
This property was only required for compatibility reasons in the pc-1.0 machine type and earlier. Now that these machine types have been removed, the property is not useful anymore. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210203171832.483176-4-thuth@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: David Hildenbrand <david@redhat.com>
2021-02-05hw/i386: Remove the deprecated pc-1.x machine typesThomas Huth1-94/+0
They have been deprecated since QEMU v5.0, time to remove them now. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210203171832.483176-2-thuth@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2021-02-05vhost: Unbreak SMMU and virtio-iommu on dev-iotlb supportPeter Xu3-2/+21
Previous work on dev-iotlb message broke vhost on either SMMU or virtio-iommu since dev-iotlb (or PCIe ATS) is not yet supported for those archs. An initial idea is that we can let IOMMU to export this information to vhost so that vhost would know whether the vIOMMU would support dev-iotlb, then vhost can conditionally register to dev-iotlb or the old iotlb way. We can work based on some previous patch to introduce PCIIOMMUOps as Yi Liu proposed [1]. However it's not as easy as I thought since vhost_iommu_region_add() does not have a PCIDevice context at all since it's completely a backend. It seems non-trivial to pass over a PCI device to the backend during init. E.g. when the IOMMU notifier registered hdev->vdev is still NULL. To make the fix smaller and easier, this patch goes the other way to leverage the flag_changed() hook of vIOMMUs so that SMMU and virtio-iommu can trap the dev-iotlb registration and fail it. Then vhost could try the fallback solution as using UNMAP invalidation for it's translations. [1] https://lore.kernel.org/qemu-devel/1599735398-6829-4-git-send-email-yi.l.liu@intel.com/ Reported-by: Eric Auger <eric.auger@redhat.com> Fixes: b68ba1ca57677acf870d5ab10579e6105c1f5338 Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20210204191228.187550-1-peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-05virtio-pmem: add trace eventsPankaj Gupta2-0/+9
This patch adds trace events for virtio-pmem functionality. Adding trace events for virtio pmem request, reponse and host side fsync functionality. Signed-off-by: Pankaj Gupta <pankaj.gupta.linux@gmail.com> Message-Id: <20201117115705.32195-1-pankaj.gupta.linux@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-05virtio: Add corresponding memory_listener_unregister to unrealizeEugenio Pérez1-1/+1
Address space is destroyed without proper removal of its listeners with current code. They are expected to be removed in virtio_device_instance_finalize [1], but qemu calls it through object_deinit, after address_space_destroy call through device_set_realized [2]. Move it to virtio_device_unrealize, called before device_set_realized [3] and making it symmetric with memory_listener_register in virtio_device_realize. v2: Delete no-op call of virtio_device_instance_finalize. Add backtraces. [1] #0 virtio_device_instance_finalize (obj=0x555557de5120) at /home/qemu/include/hw/virtio/virtio.h:71 #1 0x0000555555b703c9 in object_deinit (type=0x555556639860, obj=<optimized out>) at ../qom/object.c:671 #2 object_finalize (data=0x555557de5120) at ../qom/object.c:685 #3 object_unref (objptr=0x555557de5120) at ../qom/object.c:1184 #4 0x0000555555b4de9d in bus_free_bus_child (kid=0x555557df0660) at ../hw/core/qdev.c:55 #5 0x0000555555c65003 in call_rcu_thread (opaque=opaque@entry=0x0) at ../util/rcu.c:281 Queued by: #0 bus_remove_child (bus=0x555557de5098, child=child@entry=0x555557de5120) at ../hw/core/qdev.c:60 #1 0x0000555555b4ee31 in device_unparent (obj=<optimized out>) at ../hw/core/qdev.c:984 #2 0x0000555555b70465 in object_finalize_child_property ( obj=<optimized out>, name=<optimized out>, opaque=0x555557de5120) at ../qom/object.c:1725 #3 0x0000555555b6fa17 in object_property_del_child ( child=0x555557de5120, obj=0x555557ddcf90) at ../qom/object.c:645 #4 object_unparent (obj=0x555557de5120) at ../qom/object.c:664 #5 0x0000555555b4c071 in bus_unparent (obj=<optimized out>) at ../hw/core/bus.c:147 #6 0x0000555555b70465 in object_finalize_child_property ( obj=<optimized out>, name=<optimized out>, opaque=0x555557de5098) at ../qom/object.c:1725 #7 0x0000555555b6fa17 in object_property_del_child ( child=0x555557de5098, obj=0x555557ddcf90) at ../qom/object.c:645 #8 object_unparent (obj=0x555557de5098) at ../qom/object.c:664 #9 0x0000555555b4ee19 in device_unparent (obj=<optimized out>) at ../hw/core/qdev.c:981 #10 0x0000555555b70465 in object_finalize_child_property ( obj=<optimized out>, name=<optimized out>, opaque=0x555557ddcf90) at ../qom/object.c:1725 #11 0x0000555555b6fa17 in object_property_del_child ( child=0x555557ddcf90, obj=0x55555685da10) at ../qom/object.c:645 #12 object_unparent (obj=0x555557ddcf90) at ../qom/object.c:664 #13 0x00005555558dc331 in pci_for_each_device_under_bus ( opaque=<optimized out>, fn=<optimized out>, bus=<optimized out>) at ../hw/pci/pci.c:1654 [2] Optimizer omits pci_qdev_unrealize, called by device_set_realized, and do_pci_unregister_device, called by pci_qdev_unrealize and caller of address_space_destroy. #0 address_space_destroy (as=0x555557ddd1b8) at ../softmmu/memory.c:2840 #1 0x0000555555b4fc53 in device_set_realized (obj=0x555557ddcf90, value=<optimized out>, errp=0x7fffeea8f1e0) at ../hw/core/qdev.c:850 #2 0x0000555555b6eaa6 in property_set_bool (obj=0x555557ddcf90, v=<optimized out>, name=<optimized out>, opaque=0x555556650ba0, errp=0x7fffeea8f1e0) at ../qom/object.c:2255 #3 0x0000555555b70e07 in object_property_set ( obj=obj@entry=0x555557ddcf90, name=name@entry=0x555555db99df "realized", v=v@entry=0x7fffe46b7500, errp=errp@entry=0x5555565bbf38 <error_abort>) at ../qom/object.c:1400 #4 0x0000555555b73c5f in object_property_set_qobject ( obj=obj@entry=0x555557ddcf90, name=name@entry=0x555555db99df "realized", value=value@entry=0x7fffe44f6180, errp=errp@entry=0x5555565bbf38 <error_abort>) at ../qom/qom-qobject.c:28 #5 0x0000555555b71044 in object_property_set_bool ( obj=0x555557ddcf90, name=0x555555db99df "realized", value=<optimized out>, errp=0x5555565bbf38 <error_abort>) at ../qom/object.c:1470 #6 0x0000555555921cb7 in pcie_unplug_device (bus=<optimized out>, dev=0x555557ddcf90, opaque=<optimized out>) at /home/qemu/include/hw/qdev-core.h:17 #7 0x00005555558dc331 in pci_for_each_device_under_bus ( opaque=<optimized out>, fn=<optimized out>, bus=<optimized out>) at ../hw/pci/pci.c:1654 [3] #0 virtio_device_unrealize (dev=0x555557de5120) at ../hw/virtio/virtio.c:3680 #1 0x0000555555b4fc63 in device_set_realized (obj=0x555557de5120, value=<optimized out>, errp=0x7fffee28df90) at ../hw/core/qdev.c:850 #2 0x0000555555b6eab6 in property_set_bool (obj=0x555557de5120, v=<optimized out>, name=<optimized out>, opaque=0x555556650ba0, errp=0x7fffee28df90) at ../qom/object.c:2255 #3 0x0000555555b70e17 in object_property_set ( obj=obj@entry=0x555557de5120, name=name@entry=0x555555db99ff "realized", v=v@entry=0x7ffdd8035040, errp=errp@entry=0x5555565bbf38 <error_abort>) at ../qom/object.c:1400 #4 0x0000555555b73c6f in object_property_set_qobject ( obj=obj@entry=0x555557de5120, name=name@entry=0x555555db99ff "realized", value=value@entry=0x7ffdd8035020, errp=errp@entry=0x5555565bbf38 <error_abort>) at ../qom/qom-qobject.c:28 #5 0x0000555555b71054 in object_property_set_bool ( obj=0x555557de5120, name=name@entry=0x555555db99ff "realized", value=value@entry=false, errp=0x5555565bbf38 <error_abort>) at ../qom/object.c:1470 #6 0x0000555555b4edc5 in qdev_unrealize (dev=<optimized out>) at ../hw/core/qdev.c:403 #7 0x0000555555b4c2a9 in bus_set_realized (obj=<optimized out>, value=<optimized out>, errp=<optimized out>) at ../hw/core/bus.c:204 #8 0x0000555555b6eab6 in property_set_bool (obj=0x555557de5098, v=<optimized out>, name=<optimized out>, opaque=0x555557df04c0, errp=0x7fffee28e0a0) at ../qom/object.c:2255 #9 0x0000555555b70e17 in object_property_set ( obj=obj@entry=0x555557de5098, name=name@entry=0x555555db99ff "realized", v=v@entry=0x7ffdd8034f50, errp=errp@entry=0x5555565bbf38 <error_abort>) at ../qom/object.c:1400 #10 0x0000555555b73c6f in object_property_set_qobject ( obj=obj@entry=0x555557de5098, name=name@entry=0x555555db99ff "realized", value=value@entry=0x7ffdd8020630, errp=errp@entry=0x5555565bbf38 <error_abort>) at ../qom/qom-qobject.c:28 #11 0x0000555555b71054 in object_property_set_bool ( obj=obj@entry=0x555557de5098, name=name@entry=0x555555db99ff "realized", value=value@entry=false, errp=0x5555565bbf38 <error_abort>) at ../qom/object.c:1470 #12 0x0000555555b4c725 in qbus_unrealize ( bus=bus@entry=0x555557de5098) at ../hw/core/bus.c:178 #13 0x0000555555b4fc00 in device_set_realized (obj=0x555557ddcf90, value=<optimized out>, errp=0x7fffee28e1e0) at ../hw/core/qdev.c:844 #14 0x0000555555b6eab6 in property_set_bool (obj=0x555557ddcf90, v=<optimized out>, name=<optimized out>, opaque=0x555556650ba0, errp=0x7fffee28e1e0) at ../qom/object.c:2255 #15 0x0000555555b70e17 in object_property_set ( obj=obj@entry=0x555557ddcf90, name=name@entry=0x555555db99ff "realized", v=v@entry=0x7ffdd8020560, errp=errp@entry=0x5555565bbf38 <error_abort>) at ../qom/object.c:1400 #16 0x0000555555b73c6f in object_property_set_qobject ( obj=obj@entry=0x555557ddcf90, name=name@entry=0x555555db99ff "realized", value=value@entry=0x7ffdd8020540, errp=errp@entry=0x5555565bbf38 <error_abort>) at ../qom/qom-qobject.c:28 #17 0x0000555555b71054 in object_property_set_bool ( obj=0x555557ddcf90, name=0x555555db99ff "realized", value=<optimized out>, errp=0x5555565bbf38 <error_abort>) at ../qom/object.c:1470 #18 0x0000555555921cb7 in pcie_unplug_device (bus=<optimized out>, dev=0x555557ddcf90, opaque=<optimized out>) at /home/qemu/include/hw/qdev-core.h:17 #19 0x00005555558dc331 in pci_for_each_device_under_bus ( opaque=<optimized out>, fn=<optimized out>, bus=<optimized out>) at ../hw/pci/pci.c:1654 Fixes: c611c76417f ("virtio: add MemoryListener to cache ring translations") Buglink: https://bugs.launchpad.net/qemu/+bug/1912846 Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Message-Id: <20210125192505.390554-1-eperezma@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-05virtio-mmio: fix guest kernel crash with SHM regionsLaurent Vivier1-0/+8
In the kernel, virtio_gpu_init() uses virtio_get_shm_region() since commit 6076a9711dc5 ("drm/virtio: implement blob resources: probe for host visible region") but vm_get_shm_region() unconditionally uses VIRTIO_MMIO_SHM_SEL to get the address and the length of the region. commit 38e895487afc ("virtio: Implement get_shm_region for MMIO transport" As this is not implemented in QEMU, address and length are 0 and passed as is to devm_request_mem_region() that triggers a crash: [drm:virtio_gpu_init] *ERROR* Could not reserve host visible region Unable to handle kernel NULL pointer dereference at virtual address (ptrval) According to the comments in the kernel, a non existent shared region has a length of (u64)-1. This is what we return now with this patch to disable the region. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201220163539.2255963-1-laurent@vivier.eu> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-05virtio: move 'use-disabled-flag' property to hw_compat_4_2Stefano Garzarella1-1/+1
Commit 9d7bd0826f introduced a new 'use-disabled-flag' property set to true by default. To allow the migration, we set this property to false in the hw_compat, but in the wrong place (hw_compat_4_1). Since commit 9d7bd0826f was released with QEMU 5.0, we move 'use-disabled-flag' property to hw_compat_4_2, so 4.2 machine types will have the pre-patch behavior and the migration can work. The issue was discovered with vhost-vsock device and 4.2 machine type without running any kernel in the VM: $ qemu-4.2 -M pc-q35-4.2,accel=kvm \ -device vhost-vsock-pci,guest-cid=4 \ -monitor stdio -incoming tcp:0:3333 $ qemu-5.2 -M pc-q35-4.2,accel=kvm \ -device vhost-vsock-pci,guest-cid=3 \ -monitor stdio (qemu) migrate -d tcp:0:3333 # qemu-4.2 output qemu-system-x86_64: Failed to load virtio-vhost_vsock:virtio qemu-system-x86_64: error while loading state for instance 0x0 of device '0000:00:03.0/virtio-vhost_vsock' qemu-system-x86_64: load of migration failed: No such file or directory Reported-by: Jing Zhao <jinzhao@redhat.com> Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1907255 Fixes: 9d7bd0826f ("virtio-pci: disable vring processing when bus-mastering is disabled") Cc: mdroth@linux.vnet.ibm.com CC: qemu-stable@nongnu.org Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20210108171252.209502-1-sgarzare@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-02-05pci: add romsize propertyPaolo Bonzini2-4/+29
This property can be useful for distros to set up known-good ROM sizes for migration purposes. The VM will fail to start if the ROM is too large, and migration compatibility will not be broken if the ROM is too small. Note that even though romsize is a uint32_t, it has to be between 1 (because empty ROM files are not accepted, and romsize must be greater than the file) and 2^31 (because values above are not powers of two and are rejected). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <20201218182736.1634344-1-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210203131828.156467-3-pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
2021-02-05pci: reject too large ROMsPaolo Bonzini1-2/+8
get_image_size() returns an int64_t, which pci_add_option_rom() assigns to an "int" without any range checking. A 32-bit BAR could be up to 2 GiB in size, so reject anything above it. In order to accomodate a rounded-up size of 2 GiB, change pci_patch_ids's size argument to unsigned. Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210203131828.156467-2-pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com>
2021-02-04display/ui: add a callback to indicate GL state is flushedMarc-André Lureau4-9/+27
Displaying rendered resources requires blocking qemu GPU to avoid extra framebuffer copies. For an external display, via Spice currently, there is a callback to block/unblock the rendering in the same thread. But with the vhost-user-gpu backend, the qemu process doesn't handle the rendering itself, and the blocking callback isn't effective. Instead, the backend must be notified when the display code is done. Fix this by adding a new GraphicHwOps callback to indicate the GL state is flushed, and we are done manipulating the shared GL resources. Call it from gtk and spice display. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210204105232.834642-19-marcandre.lureau@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-02-04virtio-gpu: avoid re-entering cmdq processingMarc-André Lureau1-0/+5
The next patch will notify the GL context got flush, which will resume the queue processing. However, if this happens within the caller context, it will end up with a stack overflow flush/update loop. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210204105232.834642-18-marcandre.lureau@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-02-04ui: add an optional get_flags callback to GraphicHwOpsMarc-André Lureau3-0/+33
Those flags can be used to express different requirements for the display or other needs. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210204105232.834642-12-marcandre.lureau@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-02-04vhost-user-gpu: add a configuration flag for dmabuf usageMarc-André Lureau1-0/+2
Let's inform VirtioGPUBase that vhost-user-gpu require DMABUF messages. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210204105232.834642-11-marcandre.lureau@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-02-04ui: remove console_has_gl_dmabuf()Marc-André Lureau1-5/+0
This check is currently limited. It only is used by vhost-user-gpu (not by vfio-display), and will print an error repeatedly during run-time. We are going to dissociate the GL context from the DisplayChangeListener, and listeners may come and go. The following patches will address this differently. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210204105232.834642-10-marcandre.lureau@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-02-04vhost-user-gpu: check backend for EDID supportMarc-André Lureau1-0/+6
EDID has been enabled by default, but the backend may not implement it (such as the contrib backend). This results in extra warnings and potentially other issues in the guest. The option shouldn't probably have been added to VIRTIO_GPU_BASE, but it's a bit too late now, report an error and disable EDID when it's not available. Fixes: 0a7196625 ("edid: flip the default to enabled") Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210204105232.834642-2-marcandre.lureau@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-02-04qxl: also notify the rendering is done when skipping itMarc-André Lureau1-0/+1
Asynchronous handlers may be waiting for the graphic_hw_update_done() to be called in this case too. Fixes: 4d6316218 ("console: add graphic_hw_update_done()") Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210201201422.446552-3-marcandre.lureau@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-02-04qxl: set qxl.ssd.dcl.con on secondary devicesMarc-André Lureau1-0/+1
On secondary QXL devices, the console is only set on qxl.vga.con. But graphic_hw_update_done() is called with qxl.ssd.dcl.con. Like for primary QXL devices, set qxl.sdd.dcl.con = qxl.vga.con. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210201201422.446552-2-marcandre.lureau@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-02-04hw/display/qxl: Fix bad printf format specifiersAlex Chen2-3/+3
We should use printf format specifier "%u" instead of "%d" for argument of type "unsigned int". Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Alex Chen <alex.chen@huawei.com> Message-id: 20201119025851.56487-1-alex.chen@huawei.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-02-03Merge remote-tracking branch ↵Peter Maydell14-68/+126
'remotes/pmaydell/tags/pull-target-arm-20210203' into staging target-arm queue: * hw/intc/arm_gic: Allow to use QTest without crashing * hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled * hw/char/exynos4210_uart: Fix missing call to report ready for input * hw/arm/smmuv3: Fix addr_mask for range-based invalidation * hw/ssi/imx_spi: Fix various minor bugs * hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register * hw/arm: Add missing Kconfig dependencies * hw/arm: Display CPU type in machine description # gpg: Signature made Wed 03 Feb 2021 10:16:36 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210203: (21 commits) hw/arm: Display CPU type in machine description hw/net/can: ZynqMP CAN device requires PTIMER hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals hw/arm/xlnx-versal: Versal SoC requires ZDMA hw/arm/exynos4210: Add missing dependency on OR_IRQ hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register hw/ssi: imx_spi: Correct tx and rx fifo endianness hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Round up the burst length to be multiple of 8 hw/ssi: imx_spi: Disable chip selects when controller is disabled hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value hw/ssi: imx_spi: Remove pointless variable initialization hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/arm/smmuv3: Fix addr_mask for range-based invalidation hw/char/exynos4210_uart: Fix missing call to report ready for input hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-03hw/arm: Display CPU type in machine descriptionPhilippe Mathieu-Daudé6-7/+7
Most of ARM machines display their CPU when QEMU list the available machines (-M help). Some machines do not. Fix to unify the help output. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210131184449.382425-7-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-03hw/net/can: ZynqMP CAN device requires PTIMERPhilippe Mathieu-Daudé1-0/+1
Add a dependency XLNX_ZYNQMP -> PTIMER to fix: /usr/bin/ld: libcommon.fa.p/hw_net_can_xlnx-zynqmp-can.c.o: in function `xlnx_zynqmp_can_realize': hw/net/can/xlnx-zynqmp-can.c:1082: undefined reference to `ptimer_init' hw/net/can/xlnx-zynqmp-can.c:1085: undefined reference to `ptimer_transaction_begin' hw/net/can/xlnx-zynqmp-can.c:1087: undefined reference to `ptimer_set_freq' hw/net/can/xlnx-zynqmp-can.c:1088: undefined reference to `ptimer_set_limit' hw/net/can/xlnx-zynqmp-can.c:1089: undefined reference to `ptimer_run' hw/net/can/xlnx-zynqmp-can.c:1090: undefined reference to `ptimer_transaction_commit' libcommon.fa.p/hw_net_can_xlnx-zynqmp-can.c.o:(.data.rel+0x2c8): undefined reference to `vmstate_ptimer' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210131184449.382425-6-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-03hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripheralsPhilippe Mathieu-Daudé1-0/+1
The Versal SoC instantiates the TYPE_XLNX_ZYNQMP_RTC object in versal_create_rtc()(). Select CONFIG_XLNX_ZYNQMP to fix: $ make check-qtest-aarch64 ... Running test qtest-aarch64/qom-test qemu-system-aarch64: missing object type 'xlnx-zynmp.rtc' Broken pipe Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210131184449.382425-5-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-03hw/arm/xlnx-versal: Versal SoC requires ZDMAPhilippe Mathieu-Daudé3-1/+6
The Versal SoC instantiates the TYPE_XLNX_ZDMA object in versal_create_admas(). Introduce the XLNX_ZDMA configuration and select it to fix: $ qemu-system-aarch64 -M xlnx-versal-virt ... qemu-system-aarch64: missing object type 'xlnx.zdma' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210131184449.382425-4-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-03hw/arm/exynos4210: Add missing dependency on OR_IRQPhilippe Mathieu-Daudé1-0/+1
The Exynos4210 SoC uses an OR gate on the PL330 IRQ lines. Fixes: dab15fbe2ab ("hw/arm/exynos4210: Fix DMA initialization") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210131184449.382425-3-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-03hw/arm/stm32f405_soc: Add missing dependency on OR_IRQPhilippe Mathieu-Daudé1-0/+1
The STM32F405 SoC uses an OR gate on its ADC IRQs. Fixes: 529fc5fd3e1 ("hw/arm: Add the STM32F4xx SoC") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210131184449.382425-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR registerPhilippe Mathieu-Daudé1-1/+1
Per the ARM Generic Interrupt Controller Architecture specification (document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit, not 10: - 4.3 Distributor register descriptions - 4.3.15 Software Generated Interrupt Register, GICD_SG - Table 4-21 GICD_SGIR bit assignments The Interrupt ID of the SGI to forward to the specified CPU interfaces. The value of this field is the Interrupt ID, in the range 0-15, for example a value of 0b0011 specifies Interrupt ID 3. Correct the irq mask to fix an undefined behavior (which eventually lead to a heap-buffer-overflow, see [Buglink]): $ echo 'writel 0x8000f00 0xff4affb0' | qemu-system-aarch64 -M virt,accel=qtest -qtest stdio [I 1612088147.116987] OPENED [R +0.278293] writel 0x8000f00 0xff4affb0 ../hw/intc/arm_gic.c:1498:13: runtime error: index 944 out of bounds for type 'uint8_t [16][8]' SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../hw/intc/arm_gic.c:1498:13 This fixes a security issue when running with KVM on Arm with kernel-irqchip=off. (The default is kernel-irqchip=on, which is unaffected, and which is also the correct choice for performance.) Cc: qemu-stable@nongnu.org Fixes: CVE-2021-20221 Fixes: 9ee6e8bb853 ("ARMv7 support.") Buglink: https://bugs.launchpad.net/qemu/+bug/1913916 Buglink: https://bugs.launchpad.net/qemu/+bug/1913917 Reported-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210131103401.217160-1-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/ssi: imx_spi: Correct tx and rx fifo endiannessBin Meng1-5/+2
The endianness of data exchange between tx and rx fifo is incorrect. Earlier bytes are supposed to show up on MSB and later bytes on LSB, ie: in big endian. The manual does not explicitly say this, but the U-Boot and Linux driver codes have a swap on the data transferred to tx fifo and from rx fifo. With this change, U-Boot read from / write to SPI flash tests pass. => sf test 1ff000 1000 SPI flash test: 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Test passed 0 erase: 0 ticks, 4096000 KiB/s 32768.000 Mbps 1 check: 3 ticks, 1333 KiB/s 10.664 Mbps 2 write: 235 ticks, 17 KiB/s 0.136 Mbps 3 read: 2 ticks, 2000 KiB/s 16.000 Mbps Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210129132323.30946-11-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logicBin Meng1-1/+1
For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word. 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word. Current logic uses either s->burst_length or 32, whichever smaller, to determine how many bits it should read from the tx fifo each time. For example, for a 48 bit burst length, current logic transfers the first 32 bit from the first word in the tx fifo, followed by a 16 bit from the second word in the tx fifo, which is wrong. The correct logic should be: transfer the first 16 bit from the first word in the tx fifo, followed by a 32 bit from the second word in the tx fifo. With this change, SPI flash can be successfully probed by U-Boot on imx6 sabrelite board. => sf probe SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210129132323.30946-10-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/ssi: imx_spi: Round up the burst length to be multiple of 8Bin Meng1-1/+16
Current implementation of the imx spi controller expects the burst length to be multiple of 8, which is the most common use case. In case the burst length is not what we expect, log it to give user a chance to notice it, and round it up to be multiple of 8. Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-id: 20210129132323.30946-9-bmeng.cn@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/ssi: imx_spi: Disable chip selects when controller is disabledXuzhou Cheng1-0/+6
When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_soft_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210129132323.30946-8-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabledPhilippe Mathieu-Daudé1-4/+9
When the block is disabled, only the ECSPI_CONREG register can be modified. Setting the EN bit enabled the device, clearing it "disables the block and resets the internal logic with the exception of the ECSPI_CONREG" register. Ignore all other registers write except ECSPI_CONREG when the block is disabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210129132323.30946-7-bmeng.cn@gmail.com Message-Id: <20210115153049.3353008-6-f4bug@amsat.org> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabledPhilippe Mathieu-Daudé1-31/+29
When the block is disabled, it stay it is 'internal reset logic' (internal clocks are gated off). Reading any register returns its reset value. Only update this value if the device is enabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-id: 20210129132323.30946-6-bmeng.cn@gmail.com Message-Id: <20210115153049.3353008-5-f4bug@amsat.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register valuePhilippe Mathieu-Daudé1-8/+24
When the block is disabled, all registers are reset with the exception of the ECSPI_CONREG. It is initialized to zero when the instance is created. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210129132323.30946-5-bmeng.cn@gmail.com [bmeng: add a 'common_reset' function that does most of reset operation] Signed-off-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/ssi: imx_spi: Remove pointless variable initializationPhilippe Mathieu-Daudé1-2/+0
'burst_length' is cleared in imx_spi_reset(), which is called after imx_spi_realize(). Remove the initialization to simplify. Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-id: 20210129132323.30946-4-bmeng.cn@gmail.com Message-Id: <20210115153049.3353008-3-f4bug@amsat.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()Bin Meng1-4/+10
Usually the approach is that the device on the other end of the line is going to reset its state anyway, so there's no need to actively signal an irq line change during the reset hook. Move imx_spi_update_irq() out of imx_spi_reset(), to a new function imx_spi_soft_reset() that is called when the controller is disabled. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210129132323.30946-3-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/ssi: imx_spi: Use a macro for number of chip selects supportedBin Meng1-2/+2
Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-id: 20210129132323.30946-2-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/arm/smmuv3: Fix addr_mask for range-based invalidationZenghui Yu1-1/+3
When handling guest range-based IOTLB invalidation, we should decode the TG field into the corresponding translation granule size so that we can pass the correct invalidation range to backend. Set @granule to (tg * 2 + 10) to properly emulate the architecture. Fixes: d52915616c05 ("hw/arm/smmuv3: Get prepared for range invalidation") Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Acked-by: Eric Auger <eric.auger@redhat.com> Message-id: 20210130043220.1345-1-yuzenghui@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/char/exynos4210_uart: Fix missing call to report ready for inputIris Johnson1-0/+1
When the frontend device has no space for a read the fd is removed from polling to allow time for the guest to read and clear the buffer. Without the call to qemu_chr_fe_accept_input(), the poll will not be broken out of when the guest has cleared the buffer causing significant IO delays that get worse with smaller buffers. Buglink: https://bugs.launchpad.net/qemu/+bug/1913341 Signed-off-by: Iris Johnson <iris@modwiz.com> Message-id: 20210130184016.1787097-1-iris@modwiz.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabledIris Johnson1-1/+5
Currently the Exynos 4210 UART code always reports available FIFO space when the backend checks for buffer space. When the FIFO is disabled this is behavior causes the backend chardev code to replace the data before the guest can read it. This patch changes adds the logic to report the capacity properly when the FIFO is not being used. Buglink: https://bugs.launchpad.net/qemu/+bug/1913344 Signed-off-by: Iris Johnson <iris@modwiz.com> Message-id: 20210128033655.1029577-1-iris@modwiz.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-02hw/intc/arm_gic: Allow to use QTest without crashingPhilippe Mathieu-Daudé1-1/+2
Alexander reported an issue in gic_get_current_cpu() using the fuzzer. Yet another "deref current_cpu with QTest" bug, reproducible doing: $ echo readb 0xf03ff000 | qemu-system-arm -M npcm750-evb,accel=qtest -qtest stdio [I 1611849440.651452] OPENED [R +0.242498] readb 0xf03ff000 hw/intc/arm_gic.c:63:29: runtime error: member access within null pointer of type 'CPUState' (aka 'struct CPUState') SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior hw/intc/arm_gic.c:63:29 in AddressSanitizer:DEADLYSIGNAL ================================================================= ==3719691==ERROR: AddressSanitizer: SEGV on unknown address 0x0000000082a0 (pc 0x5618790ac882 bp 0x7ffca946f4f0 sp 0x7ffca946f4a0 T0) ==3719691==The signal is caused by a READ memory access. #0 0x5618790ac882 in gic_get_current_cpu hw/intc/arm_gic.c:63:29 #1 0x5618790a8901 in gic_dist_readb hw/intc/arm_gic.c:955:11 #2 0x5618790a7489 in gic_dist_read hw/intc/arm_gic.c:1158:17 #3 0x56187adc573b in memory_region_read_with_attrs_accessor softmmu/memory.c:464:9 #4 0x56187ad7903a in access_with_adjusted_size softmmu/memory.c:552:18 #5 0x56187ad766d6 in memory_region_dispatch_read1 softmmu/memory.c:1426:16 #6 0x56187ad758a8 in memory_region_dispatch_read softmmu/memory.c:1449:9 #7 0x56187b09e84c in flatview_read_continue softmmu/physmem.c:2822:23 #8 0x56187b0a0115 in flatview_read softmmu/physmem.c:2862:12 #9 0x56187b09fc9e in address_space_read_full softmmu/physmem.c:2875:18 #10 0x56187aa88633 in address_space_read include/exec/memory.h:2489:18 #11 0x56187aa88633 in qtest_process_command softmmu/qtest.c:558:13 #12 0x56187aa81881 in qtest_process_inbuf softmmu/qtest.c:797:9 #13 0x56187aa80e02 in qtest_read softmmu/qtest.c:809:5 current_cpu is NULL because QTest accelerator does not use CPU. Fix by skipping the check and returning the first CPU index when QTest accelerator is used, similarly to commit c781a2cc423 ("hw/i386/vmport: Allow QTest use without crashing"). Reported-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Darren Kenny <darren.kenny@oracle.com> Reviewed-by: Alexander Bulekov <alxndr@bu.edu> Message-id: 20210128161417.3726358-1-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-01nvdimm: check -object memory-backend-file, readonly=on optionStefan Hajnoczi1-0/+9
Check that -device nvdimm,unarmed=on is used when -object memory-backend-file,readonly=on and document that -device nvdimm,unarmed=on|off controls whether the NVDIMM appears read-only to the guest. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Liam Merwick <liam.merwick@oracle.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20210104171320.575838-4-stefanha@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2021-01-29hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYSPeter Maydell1-10/+0
Now that the watchdog device uses its Clock input rather than being passed the value of system_clock_scale at creation time, we can remove the hack where we reset the STELLARIS_SYS at board creation time to force it to set system_clock_scale. Instead it will be reset at the usual point in startup and will inform the watchdog of the clock frequency at that point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210128114145.20536-26-peter.maydell@linaro.org Message-id: 20210121190622.22000-26-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-29arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSEPeter Maydell4-20/+0
Now no users are setting the frq properties on the CMSDK timer, dualtimer, watchdog or ARMSSE SoC devices, we can remove the properties and the struct fields that back them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210128114145.20536-25-peter.maydell@linaro.org Message-id: 20210121190622.22000-25-peter.maydell@linaro.org
2021-01-29arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSEPeter Maydell5-15/+0
Remove all the code that sets frequency properties on the CMSDK timer, dualtimer and watchdog devices and on the ARMSSE SoC device: these properties are unused now that the devices rely on their Clock inputs instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210128114145.20536-24-peter.maydell@linaro.org Message-id: 20210121190622.22000-24-peter.maydell@linaro.org
2021-01-29hw/arm/armsse: Use Clock to set system_clock_scalePeter Maydell1-5/+19
Use the MAINCLK Clock input to set the system_clock_scale variable rather than using the mainclk_frq property. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210128114145.20536-23-peter.maydell@linaro.org Message-id: 20210121190622.22000-23-peter.maydell@linaro.org
2021-01-29hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock inputPeter Maydell1-4/+14
Switch the CMSDK APB watchdog device over to using its Clock input; the wdogclk_frq property is now ignored. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210128114145.20536-21-peter.maydell@linaro.org Message-id: 20210121190622.22000-21-peter.maydell@linaro.org
generated by cgit v1.1 at 2025-01-28 17:43:00 +0000