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2020-12-10Clean up includesMarkus Armbruster2-2/+2
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes, with the changes to the following files manually reverted: contrib/libvhost-user/libvhost-user-glib.h contrib/libvhost-user/libvhost-user.c contrib/libvhost-user/libvhost-user.h contrib/plugins/hotblocks.c contrib/plugins/hotpages.c contrib/plugins/howvec.c contrib/plugins/lockstep.c linux-user/mips64/cpu_loop.c linux-user/mips64/signal.c linux-user/sparc64/cpu_loop.c linux-user/sparc64/signal.c linux-user/x86_64/cpu_loop.c linux-user/x86_64/signal.c target/s390x/gen-features.c tests/fp/platform.h tests/migration/s390x/a-b-bios.c tests/plugin/bb.c tests/plugin/empty.c tests/plugin/insn.c tests/plugin/mem.c tests/test-rcu-simpleq.c tests/test-rcu-slist.c tests/test-rcu-tailq.c tests/uefi-test-tools/UefiTestToolsPkg/BiosTablesTest/BiosTablesTest.c contrib/plugins/, tests/plugin/, and tests/test-rcu-slist.c appear not to include osdep.h intentionally. The remaining reverts are the same as in commit bbfff19688d. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20201113061216.2483385-1-armbru@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Acked-by: Alexander Bulekov <alxndr@bu.edu>
2020-12-10Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20201210' ↵Peter Maydell7-8/+423
into staging Aspeed patches : * New device model for EMC1413/EMC1414 temperature sensors (I2C) * New g220a-bmc Aspeed machine * couple of Aspeed cleanups # gpg: Signature made Thu 10 Dec 2020 11:58:10 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20201210: aspeed: g220a-bmc: Add an FRU aspeed/smc: Add support for address lane disablement ast2600: SRAM is 89KB aspeed: Add support for the g220a-bmc board hw/misc: add an EMC141{3,4} device model Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-12-10Merge remote-tracking branch ↵Peter Maydell3-25/+102
'remotes/kraxel/tags/microvm-20201210-pull-request' into staging microvm: add support for second ioapic # gpg: Signature made Thu 10 Dec 2020 12:13:42 GMT # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/microvm-20201210-pull-request: tests/acpi: disallow updates for expected data files tests/acpi: update expected data files tests/acpi: add ioapic2=on test for microvm tests/acpi: add data files for ioapic2 test variant tests/acpi: allow updates for expected data files microvm: add second ioapic microvm: drop microvm_gsi_handler() microvm: make pcie irq base runtime changeable microvm: make number of virtio transports runtime changeable x86: add support for second ioapic x86: rewrite gsi_handler() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-12-10hw/arm/armv7m: Correct typo in QOM object namePeter Maydell1-1/+1
Correct a typo in the name we give the NVIC object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-28-peter.maydell@linaro.org
2020-12-10hw/intc/armv7m_nvic: Implement read/write for RAS register blockPeter Maydell1-0/+56
The RAS feature has a block of memory-mapped registers at offset 0x5000 within the PPB. For a "minimal RAS" implementation we provide no error records and so the only registers that exist in the block are ERRIIDR and ERRDEVID. The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour of the "nvic-default" region is actually valid for minimal-RAS, so the main benefit of providing an explicit implementation of the register block is more accurate LOG_UNIMP messages, and a framework for where we could add a real RAS implementation later if necessary. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-27-peter.maydell@linaro.org
2020-12-10target/arm: Implement M-profile "minimal RAS implementation"Peter Maydell1-0/+13
For v8.1M the architecture mandates that CPUs must provide at least the "minimal RAS implementation" from the Reliability, Availability and Serviceability extension. This consists of: * an ESB instruction which is a NOP -- since it is in the HINT space we need only add a comment * an RFSR register which will RAZ/WI * a RAZ/WI AIRCR.IESB bit -- the code which handles writes to AIRCR does not allow setting of RES0 bits, so we already treat this as RAZ/WI; add a comment noting that this is deliberate * minimal implementation of the RAS register block at 0xe0005000 -- this will be in a subsequent commit * setting the ID_PFR0.RAS field to 0b0010 -- we will do this when we add the Cortex-M55 CPU model Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-26-peter.maydell@linaro.org
2020-12-10hw/intc/armv7m_nvic: Fix "return from inactive handler" checkPeter Maydell1-27/+32
In commit 077d7449100d824a4 we added code to handle the v8M requirement that returns from NMI or HardFault forcibly deactivate those exceptions regardless of what interrupt the guest is trying to deactivate. Unfortunately this broke the handling of the "illegal exception return because the returning exception number is not active" check for those cases. In the pseudocode this test is done on the exception the guest asks to return from, but because our implementation was doing this in armv7m_nvic_complete_irq() after the new "deactivate NMI/HardFault regardless" code we ended up doing the test on the VecInfo for that exception instead, which usually meant failing to raise the illegal exception return fault. In the case for "configurable exception targeting the opposite security state" we detected the illegal-return case but went ahead and deactivated the VecInfo anyway, which is wrong because that is the VecInfo for the other security state. Rearrange the code so that we first identify the illegal return cases, then see if we really need to deactivate NMI or HardFault instead, and finally do the deactivation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-25-peter.maydell@linaro.org
2020-12-10hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bitPeter Maydell1-8/+18
v8.1M introduces a new TRD flag in the CCR register, which enables checking for stack frame integrity signatures on SG instructions. This bit is not banked, and is always RAZ/WI to Non-secure code. Adjust the code for handling CCR reads and writes to handle this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-23-peter.maydell@linaro.org
2020-12-10target/arm: Implement v8.1M REVIDR registerPeter Maydell1-0/+5
In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc and is a read-only IMPDEF register providing implementation specific minor revision information, like the v8A REVIDR_EL1. Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-19-peter.maydell@linaro.org
2020-12-10hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1MPeter Maydell1-1/+8
The FPDSCR register has a similar layout to the FPSCR. In v8.1M it gains new fields FZ16 (if half-precision floating point is supported) and LTPSIZE (always reads as 4). Update the reset value and the code that handles writes to this register accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-16-peter.maydell@linaro.org
2020-12-10hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFaultPeter Maydell2-12/+68
For M-profile CPUs, the range from 0xe0000000 to 0xe00fffff is the Private Peripheral Bus range, which includes all of the memory mapped devices and registers that are part of the CPU itself, including the NVIC, systick timer, and debug and trace components like the Data Watchpoint and Trace unit (DWT). Within this large region, the range 0xe000e000 to 0xe000efff is the System Control Space (NVIC, system registers, systick) and 0xe002e000 to 0exe002efff is its Non-secure alias. The architecture is clear that within the SCS unimplemented registers should be RES0 for privileged accesses and generate BusFault for unprivileged accesses, and we currently implement this. It is less clear about how to handle accesses to unimplemented regions of the wider PPB. Unprivileged accesses should definitely cause BusFaults (R_DQQS), but the behaviour of privileged accesses is not given as a general rule. However, the register definitions of individual registers for components like the DWT all state that they are RES0 if the relevant component is not implemented, so the simplest way to provide that is to provide RAZ/WI for the whole range for privileged accesses. (The v7M Arm ARM does say that reserved registers should be UNK/SBZP.) Expand the container MemoryRegion that the NVIC exposes so that it covers the whole PPB space. This means: * moving the address that the ARMV7M device maps it to down by 0xe000 bytes * moving the off and the offsets within the container of all the subregions forward by 0xe000 bytes * adding a new default MemoryRegion that covers the whole container at a lower priority than anything else and which provides the RAZWI/BusFault behaviour Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-2-peter.maydell@linaro.org
2020-12-10i.MX6ul: Fix bad printf format specifiersAlex Chen1-2/+2
We should use printf format specifier "%u" instead of "%d" for argument of type "unsigned int". Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Alex Chen <alex.chen@huawei.com> Message-id: 20201126111109.112238-5-alex.chen@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-12-10i.MX6: Fix bad printf format specifiersAlex Chen2-11/+11
We should use printf format specifier "%u" instead of "%d" for argument of type "unsigned int". Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Alex Chen <alex.chen@huawei.com> Message-id: 20201126111109.112238-4-alex.chen@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-12-10i.MX31: Fix bad printf format specifiersAlex Chen2-9/+9
We should use printf format specifier "%u" instead of "%d" for argument of type "unsigned int". Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Alex Chen <alex.chen@huawei.com> Message-id: 20201126111109.112238-3-alex.chen@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-12-10i.MX25: Fix bad printf format specifiersAlex Chen1-6/+6
We should use printf format specifier "%u" instead of "%d" for argument of type "unsigned int". Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Alex Chen <alex.chen@huawei.com> Message-id: 20201126111109.112238-2-alex.chen@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-12-10sbsa-ref: allow to use Cortex-A53/57/72 cpusMarcin Juszkiewicz1-3/+20
Trusted Firmware now supports A72 on sbsa-ref by default [1] so enable it for QEMU as well. A53 was already enabled there. 1. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7117 Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201120141705.246690-1-marcin.juszkiewicz@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-12-10xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllersVikram Garhwal2-0/+54
Connect CAN0 and CAN1 on the ZynqMP. Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com> Message-id: 1605728926-352690-3-git-send-email-fnu.vikram@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-12-10hw/net/can: Introduce Xilinx ZynqMP CAN controllerVikram Garhwal5-0/+1173
The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus implementation. Bus connection and socketCAN connection for each CAN module can be set through command lines. Example for using single CAN: -object can-bus,id=canbus0 \ -machine xlnx-zcu102.canbus0=canbus0 \ -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0 Example for connecting both CAN to same virtual CAN on host machine: -object can-bus,id=canbus0 -object can-bus,id=canbus1 \ -machine xlnx-zcu102.canbus0=canbus0 \ -machine xlnx-zcu102.canbus1=canbus1 \ -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0 \ -object can-host-socketcan,id=socketcan1,if=vcan0,canbus=canbus1 To create virtual CAN on the host machine, please check the QEMU CAN docs: https://github.com/qemu/qemu/blob/master/docs/can.txt Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com> Message-id: 1605728926-352690-2-git-send-email-fnu.vikram@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-12-10hw/arm/smmuv3: Fix up L1STD_SPAN decodingKunkun Jiang1-1/+1
Accroding to the SMMUv3 spec, the SPAN field of Level1 Stream Table Descriptor is 5 bits([4:0]). Fixes: 9bde7f0674f(hw/arm/smmuv3: Implement translate callback) Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com> Message-id: 20201124023711.1184-1-jiangkunkun@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-12-10aspeed: g220a-bmc: Add an FRUJohn Wang1-0/+12
Add an eeprom device and fill it with fru information $ ipmitool fru print 0 Product Manufacturer : Bytedance Product Name : G220A Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20201210103607.556-1-wangzhiqiang.bj@bytedance.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-12-10aspeed/smc: Add support for address lane disablementCédric Le Goater1-7/+18
The controller can be configured to disable or enable address and data byte lanes when issuing commands. This is useful in read command mode to send SPI NOR commands that don't have an address space, such as RDID. It's a good way to have a unified read operation for registers and flash contents accesses. A new SPI driver proposed by Aspeed makes use of this feature. Add support for address lanes to start with. We will do the same for the data lanes if they are controlled one day. Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20201120161547.740806-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-12-10ast2600: SRAM is 89KBJoel Stanley1-1/+1
On the AST2600A1, the SRAM size was increased to 89KB. Fixes: 7582591ae745 ("aspeed: Support AST2600A1 silicon revision") Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20201112012113.835858-1-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-12-10aspeed: Add support for the g220a-bmc boardJohn Wang1-0/+60
G220A is a 2 socket x86 motherboard supported by OpenBMC. Strapping configuration was obtained from hardware. Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20201122105134.671-2-wangzhiqiang.bj@bytedance.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-12-10hw/misc: add an EMC141{3,4} device modelJohn Wang4-0/+332
Largely inspired by the TMP421 temperature sensor, here is a model for the EMC1413/EMC1414 temperature sensors. Specs can be found here : http://ww1.microchip.com/downloads/en/DeviceDoc/20005274A.pdf Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20201122105134.671-1-wangzhiqiang.bj@bytedance.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-12-10microvm: add second ioapicGerd Hoffmann1-5/+51
Create second ioapic, route virtio-mmio IRQs to it, allow more virtio-mmio devices (24 instead of 8). Needs ACPI, enabled by default, can be turned off using -machine ioapic2=off Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-8-kraxel@redhat.com
2020-12-10microvm: drop microvm_gsi_handler()Gerd Hoffmann1-13/+1
With the improved gsi_handler() we don't need our private version any more. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-7-kraxel@redhat.com
2020-12-10microvm: make pcie irq base runtime changeableGerd Hoffmann1-5/+6
Allows to move them in case we have enough irq lines available. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-6-kraxel@redhat.com
2020-12-10microvm: make number of virtio transports runtime changeableGerd Hoffmann1-2/+7
This will allow to increase the number of transports in case we have enough irq lines available for them all. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-5-kraxel@redhat.com
2020-12-10x86: add support for second ioapicGerd Hoffmann2-0/+31
Add ioapic_init_secondary to initialize it, wire up in gsi handling and acpi apic table creation. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-4-kraxel@redhat.com
2020-12-10x86: rewrite gsi_handler()Gerd Hoffmann1-4/+10
Rewrite function to use switch() for IRQ number mapping. Check i8259_irq exists before raising it so the function also works in case no i8259 (aka pic) is present. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20201203105423.10431-3-kraxel@redhat.com
2020-12-09Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell29-678/+897
pc,pci,virtio: fixes, cleanups Lots of fixes, cleanups. CPU hot-unplug improvements. A new AER property for virtio devices, adding a dummy AER capability. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed 09 Dec 2020 18:04:28 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (65 commits) hw/virtio-pci Added AER capability. hw/virtio-pci Added counter for pcie capabilities offsets. pcie_aer: Fix help message of pcie_aer_inject_error command x86: ich9: let firmware negotiate 'CPU hot-unplug with SMI' feature x86: ich9: factor out "guest_cpu_hotplug_features" tests/acpi: update expected files x86: acpi: let the firmware handle pending "CPU remove" events in SMM tests/acpi: allow expected files change x86: acpi: introduce AcpiPmInfo::smi_on_cpu_unplug acpi: cpuhp: introduce 'firmware performs eject' status/control bits hw/i386/pc: add max combined fw size as machine configuration option block/export: avoid g_return_val_if() input validation contrib/vhost-user-input: avoid g_return_val_if() input validation contrib/vhost-user-gpu: avoid g_return_val_if() input validation contrib/vhost-user-blk: avoid g_return_val_if() input validation .gitlab-ci: add build-libvhost-user libvhost-user: add a simple link test without glib libvhost-user: make it a meson subproject libvhost-user: drop qemu/osdep.h dependency libvhost-user: remove qemu/compiler.h usage ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-12-09hw/virtio-pci Added AER capability.Andrew Melnychenko2-0/+20
Added AER capability for virtio-pci devices. Also added property for devices, by default AER is disabled. Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Message-Id: <20201203110713.204938-3-andrew@daynix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-09hw/virtio-pci Added counter for pcie capabilities offsets.Andrew Melnychenko1-1/+3
Removed hardcoded offset for ats. Added cap offset counter for future capabilities like AER. Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Message-Id: <20201203110713.204938-2-andrew@daynix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-09x86: ich9: let firmware negotiate 'CPU hot-unplug with SMI' featureIgor Mammedov2-2/+10
Keep CPU hotunplug with SMI disabled on 5.2 and older and enable it by default on newer machine types. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20201207140739.3829993-9-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-09x86: ich9: factor out "guest_cpu_hotplug_features"Igor Mammedov1-2/+6
it will be reused by next patch to check validity of unplug feature. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20201207140739.3829993-8-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-09x86: acpi: let the firmware handle pending "CPU remove" events in SMMIgor Mammedov2-2/+13
if firmware and QEMU negotiated CPU hotunplug support, generate _EJ0 method so that it will mark CPU for removal by firmware and pass control to it by triggering SMI. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20201207140739.3829993-6-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-09x86: acpi: introduce AcpiPmInfo::smi_on_cpu_unplugIgor Mammedov1-0/+4
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20201207140739.3829993-4-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-09acpi: cpuhp: introduce 'firmware performs eject' status/control bitsIgor Mammedov2-1/+13
Adds bit #4 to status/control field of CPU hotplug MMIO interface. New bit will be used OSPM to mark CPUs as pending for removal by firmware, when it calls _EJ0 method on CPU device node. Later on, when firmware sees this bit set, it will perform CPU eject which will clear bit #4 as well. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20201207140739.3829993-3-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-09hw/i386/pc: add max combined fw size as machine configuration optionErich-McMillan2-12/+54
At Hewlett Packard Inc. we have a need for increased fw size to enable testing of our custom fw. Rebase v6 patch to d73c46e4 Signed-off-by: Erich McMillan <erich.mcmillan@hp.com> Message-Id: <20201208155338.14-1-erich.mcmillan@hp.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-09hw/m68k/mcf5206: Don't leak IRQs in mcf5206_mbar_realize()Peter Maydell1-6/+6
Coverity points out that the realize function for the TYPE_MCF5206_MBAR device leaks the IRQ array it allocates with qemu_allocate_irqs(). Keep a pointer to it in the device state struct to avoid the leak. (Since it needs to stay around for the life of the simulation there is no need to actually free it, and the leak was harmless.) Fixes: Coverity CID 1432412 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201120172314.14725-1-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-12-08hw: add compat machines for 6.0Cornelia Huck7-6/+65
Add 6.0 machine types for arm/i440fx/q35/s390x/spapr. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20201109173928.1001764-1-cohuck@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-08failover: Remove primary_dev memberJuan Quintela1-31/+24
Only three uses remained, and we can remove them on that case. Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <20201118083748.1328-28-quintela@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-08failover: simplify failover_unplug_primaryJuan Quintela1-15/+10
We can calculate device just once. Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <20201118083748.1328-27-quintela@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-08failover: Caller of this two functions already have primary_devJuan Quintela1-13/+14
Pass it as an argument. Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <20201118083748.1328-26-quintela@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-08failover: We don't need to cache primary_device_id anymoreJuan Quintela1-10/+10
Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <20201118083748.1328-25-quintela@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-08failover: split failover_find_primary_device_id()Juan Quintela1-16/+47
So we can calculate the device id when we need it. Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <20201118083748.1328-24-quintela@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-08failover: remove failover_find_primary_device() error parameterJuan Quintela1-6/+3
It can never give one error. Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <20201118083748.1328-23-quintela@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-08failover: make sure that id always existJuan Quintela1-3/+0
We check that it exist at device creation time, so we don't have to check anywhere else. Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <20201118083748.1328-22-quintela@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-08failover: Rename to failover_find_primary_device()Juan Quintela1-3/+9
This commit: * Rename them to failover_find_primary_devices() so - it starts with failover_ - it don't connect anything, just find the primary device * Create documentation for the function Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <20201118083748.1328-19-quintela@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-12-08failover: virtio_net_connect_failover_devices() does nothingJuan Quintela1-15/+2
It just calls virtio_net_find_primary(), so just update the callers. Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <20201118083748.1328-18-quintela@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.1 at 2025-09-19 19:22:27 +0000