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2020-10-28spapr: Use appropriate getter for PC_DIMM_ADDR_PROPGreg Kurz1-2/+2
The PC_DIMM_ADDR_PROP property is defined as: DEFINE_PROP_UINT64(PC_DIMM_ADDR_PROP, PCDIMMDevice, addr, 0), Use object_property_get_uint() instead of object_property_get_int(). Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <160309729609.2739814.4996614957953215591.stgit@bahia.lan> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-10-28pc-dimm: Drop @errp argument of pc_dimm_plug()Greg Kurz4-21/+4
pc_dimm_plug() doesn't use it. It only aborts on error. Drop @errp and adapt the callers accordingly. [dwg: Removed unused label to fix compile] Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <160309728447.2739814.12831204841251148202.stgit@bahia.lan> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-10-28spapr: Simplify spapr_cpu_core_realize() and spapr_cpu_core_unrealize()Greg Kurz1-13/+3
Now that the error path of spapr_cpu_core_realize() is just to call idempotent spapr_cpu_core_unrealize() for rollback, no need to create and realize the vCPUs in two separate loops. Merge them and do them same in spapr_cpu_core_unrealize() for symmetry. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <160279673321.1808373.2248221100790367912.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-10-28spapr: Make spapr_cpu_core_unrealize() idempotentGreg Kurz1-20/+21
spapr_cpu_core_realize() has a rollback path which partially duplicates the code of spapr_cpu_core_unrealize(). Let's make spapr_cpu_core_unrealize() idempotent and call it instead. This requires to: - move the registration and unregistration of the reset handler around but it is harmless, - allocate the array of vCPUs with g_new0() to be able to filter out unused slots, - make sure to only unrealize vCPUs that have been already realized. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <160279672626.1808373.14142129300586424514.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-10-28spapr: Drop spapr_delete_vcpu() unused argumentGreg Kurz1-3/+3
The 'sc' argument is unused. Drop it. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <160279671929.1808373.10333672533575251075.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-10-28spapr: Unrealize vCPUs with qdev_unrealize()Greg Kurz1-2/+2
Since we introduced CPU hot-unplug in sPAPR, we don't unrealize the vCPU objects explicitly. Instead, we let QOM handle that for us under object_property_del_all() when the CPU core object is finalized. The only thing we do is calling cpu_remove_sync() to tear the vCPU thread down. This happens to work but it is ugly because: - we call qdev_realize() but the corresponding qdev_unrealize() is buried deep in the QOM code - we call cpu_remove_sync() to undo qemu_init_vcpu() called by ppc_cpu_realize() in target/ppc/translate_init.c.inc - the CPU init and teardown paths aren't really symmetrical The latter didn't bite us so far but a future patch that greatly simplifies the CPU core realize path needs it to avoid a crash in QOM. For all these reasons, have ppc_cpu_unrealize() to undo the changes of ppc_cpu_realize() by calling cpu_remove_sync() at the right place, and have the sPAPR CPU core code to call qdev_unrealize(). This requires to add a missing stub because translate_init.c.inc is also compiled for user mode. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <160279671236.1808373.14732005038172874990.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-10-28spapr: Fix leak of CPU machine specific dataGreg Kurz1-10/+12
When a CPU core is being removed, the machine specific data of each CPU thread object is leaked. Fix this by calling the dedicated helper we have for that instead of simply unparenting the CPU object. Call it from a separate loop in spapr_cpu_core_unrealize() for symmetry with spapr_cpu_core_realize(). Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <160279670540.1808373.17319746576919615623.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-10-28spapr: Move spapr_create_nvdimm_dr_connectors() to core machine codeGreg Kurz2-11/+10
The spapr_create_nvdimm_dr_connectors() function doesn't need to access any internal details of the sPAPR NVDIMM implementation. Also, pretty much like for the LMBs, only spapr_machine_init() is responsible for the creation of DR connectors for NVDIMMs. Make this clear by making this function static in hw/ppc/spapr.c. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <160249772183.757627.7396780936543977766.stgit@bahia.lan> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-10-28hw/net: move allocation to the heap due to very large stack frameElena Afanasova1-2/+3
[dwg] The stack frame itself probably isn't that big a deal, but avoiding alloca() is generally recommended these days. Signed-off-by: Elena Afanasova <eafanasova@gmail.com> Message-Id: <8f07132478469b35fb50a4706691e2b56b10a67b.camel@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-10-28ppc/spapr: re-assert IRQs during event-scan if there are pendingLaurent Vivier1-0/+12
If we hotplug a CPU during the first second of the kernel boot, the IRQ can be sent to the kernel while the RTAS event handler is not installed. The event is queued, but the kernel doesn't collect it and ignores the new CPU. As the code relies on edge-triggered IRQ, we can re-assert it during the event-scan RTAS call if there are still pending events (as it is already done in check-exception). Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20201015210318.117386-1-lvivier@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-10-28spapr: Clarify why DR connectors aren't user creatableGreg Kurz1-1/+2
DR connector is a device that emulates a firmware abstraction used by PAPR compliant guests to manage hotplug/dynamic-reconfiguration of PHBs, PCI devices, memory, and CPUs. It is internally created by the spapr platform and requires to be owned by either the machine (PHBs, CPUs, memory) or by a PHB (PCI devices). Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <160250199940.765467.6896806997161856576.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-10-27hw/timer/armv7m_systick: Rewrite to use ptimersPeter Maydell1-72/+52
The armv7m systick timer is a 24-bit decrementing, wrap-on-zero, clear-on-write counter. Our current implementation has various bugs and dubious workarounds in it (for instance see https://bugs.launchpad.net/qemu/+bug/1872237). We have an implementation of a simple decrementing counter and we put a lot of effort into making sure it handles the interesting corner cases (like "spend a cycle at 0 before reloading") -- ptimer. Rewrite the systick timer to use a ptimer rather than a raw QEMU timer. Unfortunately this is a migration compatibility break, which will affect all M-profile boards. Among other bugs, this fixes https://bugs.launchpad.net/qemu/+bug/1872237 : now writes to SYST_CVR when the timer is enabled correctly do nothing; when the timer is enabled via SYST_CSR.ENABLE, the ptimer code will (because of POLICY_NO_IMMEDIATE_RELOAD) arrange that after one timer tick the counter is reloaded from SYST_RVR and then counts down from there, as the architecture requires. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201015151829.14656-3-peter.maydell@linaro.org
2020-10-27hw/core/ptimer: Support ptimer being disabled by timer callbackPeter Maydell1-0/+4
In ptimer_reload(), we call the callback function provided by the timer device that is using the ptimer. This callback might disable the ptimer. The code mostly handles this correctly, except that we'll still print the warning about "Timer with delta zero, disabling" if the now-disabled timer happened to be set such that it would fire again immediately if it were enabled (eg because the limit/reload value is zero). Suppress the spurious warning message and the unnecessary repeat-deletion of the underlying timer in this case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20201015151829.14656-2-peter.maydell@linaro.org
2020-10-27hw/arm/sbsa-ref: add SBSA watchdog deviceShashi Mallela1-0/+23
Included the newly implemented SBSA generic watchdog device model into SBSA platform Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201027015927.29495-3-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/watchdog: Implement SBSA watchdog deviceShashi Mallela4-0/+298
Generic watchdog device model implementation as per ARM SBSA v6.0 Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Message-id: 20201027015927.29495-2-shashi.mallela@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/bcm2835_peripherals: connect the UART clockLuc Michel1-0/+2
Connect the 'uart-out' clock from the CPRMAN to the PL011 instance. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/char/pl011: add a clock inputLuc Michel2-0/+46
Add a clock input to the PL011 UART so we can compute the current baud rate and trace it. This is intended for developers who wish to use QEMU to e.g. debug their firmware or to figure out the baud rate configured by an unknown/closed source binary. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/misc/bcm2835_cprman: add sane reset values to the registersLuc Michel1-0/+31
Those reset values have been extracted from a Raspberry Pi 3 model B v1.2, using the 2020-08-20 version of raspios. The dump was done using the debugfs interface of the CPRMAN driver in Linux (under '/sys/kernel/debug/clk'). Each exposed clock tree stage (PLLs, channels and muxes) can be observed by reading the 'regdump' file (e.g. 'plla/regdump'). Those values are set by the Raspberry Pi firmware at boot time (Linux expects them to be set when it boots up). Some stages are not exposed by the Linux driver (e.g. the PLL B). For those, the reset values are unknown and left to 0 which implies a disabled output. Once booted in QEMU, the final clock tree is very similar to the one visible on real hardware. The differences come from some unimplemented devices for which the driver simply disable the corresponding clock. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexerLuc Michel1-1/+73
This simple mux sits between the PLL channels and the DSI0E and DSI0P clock muxes. This mux selects between PLLA-DSI0 and PLLD-DSI0 channel and outputs the selected signal to source number 4 of DSI0E/P clock muxes. It is controlled by the cm_dsi0hsck register. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/misc/bcm2835_cprman: implement clock mux behaviourLuc Michel1-1/+52
A clock mux can be configured to select one of its 10 sources through the CM_CTL register. It also embeds yet another clock divider, composed of an integer part and a fractional part. The number of bits of each part is mux dependent. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/misc/bcm2835_cprman: add a clock mux skeleton implementationLuc Michel1-0/+151
The clock multiplexers are the last clock stage in the CPRMAN. Each mux outputs one clock signal that goes out of the CPRMAN to the SoC peripherals. Each mux has at most 10 sources. The sources 0 to 3 are common to all muxes. They are: 0. ground (no clock signal) 1. the main oscillator (xosc) 2. "test debug 0" clock 3. "test debug 1" clock Test debug 0 and 1 are actual clock muxes that can be used as sources to other muxes (for debug purpose). Sources 4 to 9 are mux specific and can be unpopulated (grounded). Those sources are fed by the PLL channels outputs. One corner case exists for DSI0E and DSI0P muxes. They have their source number 4 connected to an intermediate multiplexer that can select between PLLA-DSI0 and PLLD-DSI0 channel. This multiplexer is called DSI0HSCK and is not a clock mux as such. It is really a simple mux from the hardware point of view (see https://elinux.org/The_Undocumented_Pi). This mux is not implemented in this commit. Note that there is some muxes for which sources are unknown (because of a lack of documentation). For those cases all the sources are connected to ground in this implementation. Each clock mux output is exported by the CPRMAN at the qdev level, adding the suffix '-out' to the mux name to form the output clock name. (E.g. the 'uart' mux sees its output exported as 'uart-out' at the CPRMAN level.) Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/misc/bcm2835_cprman: implement PLL channels behaviourLuc Michel1-1/+32
A PLL channel is able to further divide the generated PLL frequency. The divider is given in the CTRL_A2W register. Some channels have an additional fixed divider which is always applied to the signal. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/misc/bcm2835_cprman: add a PLL channel skeleton implementationLuc Michel1-8/+147
PLLs are composed of multiple channels. Each channel outputs one clock signal. They are modeled as one device taking the PLL generated clock as input, and outputting a new clock. A channel shares the CM register with its parent PLL, and has its own A2W_CTRL register. A write to the CM register will trigger an update of the PLL and all its channels, while a write to an A2W_CTRL channel register will update the required channel only. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/misc/bcm2835_cprman: implement PLLs behaviourLuc Michel1-1/+63
The CPRMAN PLLs generate a clock based on a prescaler, a multiplier and a divider. The prescaler doubles the parent (xosc) frequency, then the multiplier/divider are applied. The multiplier has an integer and a fractional part. This commit also implements the CPRMAN CM_LOCK register. This register reports which PLL is currently locked. We consider a PLL has being locked as soon as it is enabled (on real hardware, there is a delay after turning a PLL on, for it to stabilize). Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/misc/bcm2835_cprman: add a PLL skeleton implementationLuc Michel1-0/+108
There are 5 PLLs in the CPRMAN, namely PLL A, C, D, H and B. All of them take the xosc clock as input and produce a new clock. This commit adds a skeleton implementation for the PLLs as sub-devices of the CPRMAN. The PLLs are instantiated and connected internally to the main oscillator. Each PLL has 6 registers : CM, A2W_CTRL, A2W_ANA[0,1,2,3], A2W_FRAC. A write to any of them triggers a call to the (not yet implemented) pll_update function. If the main oscillator changes frequency, an update is also triggered. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/raspi: add a skeleton implementation of the CPRMANLuc Michel4-1/+179
The BCM2835 CPRMAN is the clock manager of the SoC. It is composed of a main oscillator, and several sub-components (PLLs, multiplexers, ...) to generate the BCM2835 clock tree. This commit adds a skeleton of the CPRMAN, with a dummy register read/write implementation. It embeds the main oscillator (xosc) from which all the clocks will be derived. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/raspi: fix CPRMAN base addressLuc Michel1-2/+2
The CPRMAN (clock controller) was mapped at the watchdog/power manager address. It was also split into two unimplemented peripherals (CM and A2W) but this is really the same one, as shown by this extract of the Raspberry Pi 3 Linux device tree: watchdog@7e100000 { compatible = "brcm,bcm2835-pm\0brcm,bcm2835-pm-wdt"; [...] reg = <0x7e100000 0x114 0x7e00a000 0x24>; [...] }; [...] cprman@7e101000 { compatible = "brcm,bcm2835-cprman"; [...] reg = <0x7e101000 0x2000>; [...] }; Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/core/clock: trace clock values in Hz instead of nsLuc Michel2-5/+5
The nanosecond unit greatly limits the dynamic range we can display in clock value traces, for values in the order of 1GHz and more. The internal representation can go way beyond this value and it is quite common for today's clocks to be within those ranges. For example, a frequency between 500MHz+ and 1GHz will be displayed as 1ns. Beyond 1GHz, it will show up as 0ns. Replace nanosecond periods traces with frequencies in the Hz unit to have more dynamic range in the trace output. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27arm/trace: Fix hex printingDr. David Alan Gilbert1-1/+1
Use of 0x%d - make up our mind as 0x%x Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Eric Auger <eric.auger@redhat.com> Message-id: 20201014193355.53074-1-dgilbert@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/raspi: Add the Raspberry Pi 3 model A+Philippe Mathieu-Daudé1-0/+13
The Pi 3A+ is a stripped down version of the 3B: - 512 MiB of RAM instead of 1 GiB - no on-board ethernet chipset Add it as it is a closer match to what we model. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201024170127.3592182-10-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/raspi: Add the Raspberry Pi Zero machinePhilippe Mathieu-Daudé1-0/+13
Similarly to the Pi A, the Pi Zero uses a BCM2835 SoC (ARMv6Z core). The only difference between the revision 1.2 and 1.3 is the latter exposes a CSI camera connector. As we do not implement the Unicam peripheral, there is no point in exposing a camera connector :) Therefore we choose to model the 1.2 revision. Example booting the machine using content from [*]: $ qemu-system-arm -M raspi0 -serial stdio \ -kernel raspberrypi/firmware/boot/kernel.img \ -dtb raspberrypi/firmware/boot/bcm2708-rpi-zero.dtb \ -append 'printk.time=0 earlycon=pl011,0x20201000 console=ttyAMA0' [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST 2020 [ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d [ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache [ 0.000000] OF: fdt: Machine model: Raspberry Pi Zero ... [*] http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb Reviewed-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201024170127.3592182-9-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/raspi: Add the Raspberry Pi A+ machinePhilippe Mathieu-Daudé1-0/+13
The Pi A is almost the first machine released. It uses a BCM2835 SoC which includes a ARMv6Z core. Example booting the machine using content from [*] (we use the device tree from the B model): $ qemu-system-arm -M raspi1ap -serial stdio \ -kernel raspberrypi/firmware/boot/kernel.img \ -dtb raspberrypi/firmware/boot/bcm2708-rpi-b-plus.dtb \ -append 'earlycon=pl011,0x20201000 console=ttyAMA0' [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST 2020 [ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d [ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache [ 0.000000] OF: fdt: Machine model: Raspberry Pi Model B+ ... [*] http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201024170127.3592182-8-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/bcm2836: Introduce the BCM2835 SoCPhilippe Mathieu-Daudé2-0/+36
Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201024170127.3592182-7-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/bcm2836: Split out common realize() codePhilippe Mathieu-Daudé1-4/+18
The realize() function is clearly composed of two parts, each described by a comment: void realize() { /* common peripherals from bcm2835 */ ... /* bcm2836 interrupt controller (and mailboxes, etc.) */ ... } Split the two part, so we can reuse the common part with other SoCs from this family. Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201024170127.3592182-6-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCsPhilippe Mathieu-Daudé1-8/+7
It makes no sense to set enabled-cpus=0 on single core SoCs. Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201024170127.3592182-5-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/bcm2836: Introduce BCM283XClass::core_countPhilippe Mathieu-Daudé1-1/+4
The BCM2835 has only one core. Introduce the core_count field to be able to use values different than BCM283X_NCPUS (4). Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201024170127.3592182-4-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/bcm2836: QOM'ify more by adding class_init() to each SoC typePhilippe Mathieu-Daudé1-58/+52
Remove usage of TypeInfo::class_data. Instead fill the fields in the corresponding class_init(). So far all children use the same values for almost all fields, but we are going to add the BCM2711/BCM2838 SoC for the raspi4 machine which use different fields. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201024170127.3592182-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/bcm2836: Restrict BCM283XInfo declaration to C sourcePhilippe Mathieu-Daudé1-0/+14
No code out of bcm2836.c uses (or requires) the BCM283XInfo declarations. Move it locally to the C source file. Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201024170127.3592182-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitlyZenghui Yu1-0/+1
Ensure the vSMMUv3 will be restored before all PCIe devices so that DMA translation can work properly during migration. Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Message-id: 20201019091508.197-1-yuzenghui@huawei.com Acked-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/gpio: Add GPIO model for Nuvoton NPCM7xxHavard Skinnemoen4-0/+512
The NPCM7xx chips have multiple GPIO controllers that are mostly identical except for some minor differences like the reset values of some registers. Each controller controls up to 32 pins. Each individual pin is modeled as a pair of unnamed GPIOs -- one for emitting the actual pin state, and one for driving the pin externally. Like the nRF51 GPIO controller, a gpio level may be negative, which means the pin is not driven, or floating. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/npcm7xx: Add EHCI and OHCI controllersHavard Skinnemoen3-2/+45
The NPCM730 and NPCM750 chips have a single USB host port shared between a USB 2.0 EHCI host controller and a USB 1.1 OHCI host controller. This adds support for both of them. Testing notes: * With -device usb-kbd, qemu will automatically insert a full-speed hub, and the keyboard becomes controlled by the OHCI controller. * With -device usb-kbd,bus=usb-bus.0,port=1, the keyboard is directly attached to the port without any hubs, and the device becomes controlled by the EHCI controller since it's high speed capable. * With -device usb-kbd,bus=usb-bus.0,port=1,usb_version=1, the keyboard is directly attached to the port, but it only advertises itself as full-speed capable, so it becomes controlled by the OHCI controller. In all cases, the keyboard device enumerates correctly. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/misc: Add npcm7xx random number generatorHavard Skinnemoen4-1/+191
The RNG module returns a byte of randomness when the Data Valid bit is set. This implementation ignores the prescaler setting, and loads a new value into RNGD every time RNGCS is read while the RNG is enabled and random data is available. A qtest featuring some simple randomness tests is included. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/timer: Adding watchdog for NPCM7XX Timer.Hao Wu3-46/+260
The watchdog is part of NPCM7XX's timer module. Its behavior is controlled by the WTCR register in the timer. When enabled, the watchdog issues an interrupt signal after a pre-set amount of cycles, and issues a reset signal shortly after that. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: deleted blank line at end of npcm_watchdog_timer-test.c] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27Move npcm7xx_timer_reached_zero call out of npcm7xx_timer_pauseHavard Skinnemoen1-3/+3
This allows us to reuse npcm7xx_timer_pause for the watchdog timer. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm: fix min_cpus for xlnx-versal-virt platformPavel Dovgalyuk1-0/+1
This patch sets min_cpus field for xlnx-versal-virt platform, because it always creates XLNX_VERSAL_NR_ACPUS cpus even with -smp 1 command line option. Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 160343854912.8460.17915238517799132371.stgit@pasha-ThinkPad-X280 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/highbank: Silence warnings about missing fallthrough statementsThomas Huth1-0/+2
When compiling with -Werror=implicit-fallthrough, gcc complains about missing fallthrough annotations in this file. Looking at the code, the fallthrough is very likely intended here, so add some comments to silence the compiler warnings. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 20201020105938.23209-1-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/timer/sh_timer: Remove superfluous "break" statementsThomas Huth1-3/+0
hw_error() is marked as QEMU_NORETURN, so the "break" statements after this function are just dead code. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201020153935.54315-4-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-27hw/timer/sh_timer: Silence warnings about missing fallthrough statementsThomas Huth1-0/+4
When compiling with -Werror=implicit-fallthrough, gcc complains about missing fallthrough annotations in this file. Looking at the code, the fallthrough is very likely intended here, so add some comments to silence the compiler warnings. Fixes: cd1a3f6840e ("Stand-alone TMU emulation code") Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201020153935.54315-3-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-27hw/timer/sh_timer: Coding style clean-upThomas Huth1-32/+57
Replace TAB characters with spaces, put code after case-statement on separate lines and add some curly braces in related lines to keep checkpatch.pl happy. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201020153935.54315-2-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-26Merge remote-tracking branch 'remotes/philmd-gitlab/tags/sd-next-20201026' ↵Peter Maydell2-13/+16
into staging SD/MMC patches - Fix a bug in CMD6/SWITCH_FUNCTION (Bin Meng) - Minor housekeeping patches CI jobs result: . https://cirrus-ci.com/build/5461987880599552 . https://gitlab.com/philmd/qemu/-/pipelines/207532287 . https://travis-ci.org/github/philmd/qemu/builds/738901111 . https://app.shippable.com/github/philmd/qemu/runs/888/summary/console # gpg: Signature made Mon 26 Oct 2020 11:02:22 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/sd-next-20201026: hw/sd/sdcard: Zero out function selection fields before being populated hw/sd/sdcard: Make iolen unsigned hw/sd/sdcard: Constify sd_crc*()'s message argument hw/sd/sdcard: Simplify cmd_valid_while_locked() hw/sd/sdcard: Update the SDState documentation Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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