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2023-03-09Merge tag 'pull-aspeed-20230307' of https://github.com/legoater/qemu into ↵Peter Maydell4-9/+17
staging aspeed queue: * Small adjustments for the newest Meta machines * blk_pread_nonzeroes() fix required for pflash and m25p80 devices * Improve error reporting on file size for m25p80 devices # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmQHXi8ACgkQUaNDx8/7 # 7KHB7w//SQzcTNAUgMc6zbe3bULS9YU7csg0zX896DwQ9Ub4wtbnIps0/JwOsx6E # ss52YbbRVlHKcbahX6WW8JHtc6Wepcmnp4vC5dXdqgRryLTK5GgBu/GKcBb6qnHZ # uXwJpf7IwygOXQFg9Wy4zl3ipmrjgzMy6ZEbc3oqQUto+8E7HVMJiMXnrT5Y0yLt # Y76PywBxkYWcd522lWAXziXFxHaEJGMGrDCI/op4TuNAk0QLSRHp+x851JBF0Uyx # Lkp1cEjgADoH1FUfvo7aCNtAWGP4IFDprEupI3idPqjZ8KnnwPk2cnBMGeKJ5lWQ # XfSTwG5B3hYwGM0uYwHzHXUsq5/JGa0iDhSvjZVD8rf/w9BTek/GjypbJpL2XW6b # 4QaGGKGFWWMHbAaNVP6oEGqmkoC3QRKoQuaP6epaFyuSjNRWXkOhf5S5V10akjSc # xis0Z8gIpyLrtFT2TFc5BN9+z+PLgyaYyh7wZ2pFy1i6SOgh4FIFBOzQJDb05mmf # aFMD+6FOGx0wo8OXfy5EQyElWhVSYio+Hx9DaDP3d3cd/twHJx8nZ8QlXh2ThRd8 # jNLdFReJBImCJHSmYzbc/tGDOjg6+TWkZOzdjqTra08UwisK4XyOKj8E+sodWr0y # e/hI9nmIoarLCytMN1zElQFvj8xjpZ2lZOxr2EiX5ugYg0iuJhU= # =Xs26 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Mar 2023 15:54:23 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20230307' of https://github.com/legoater/qemu: hw/arm/aspeed: Modified BMC FRU byte data in yosemitev2 hw/arm/aspeed: Added TMP421 type sensor's support in tiogapass hw/arm/aspeed: Added TMP421 type sensor's support in yosemitev2 pflash: Fix blk_pread_nonzeroes() m25p80: Improve error when the backend file size does not match the device Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-09Merge tag 'mips-misc-20230308' of https://github.com/philmd/qemu into stagingPeter Maydell18-80/+638
MIPS (and few misc) patches - MIPS - Remove obsolete "mips" board from target-mips.rst - Fix JALS32/J32/SWM32 instructions for microMIPS - Fix CP0.Config7.WII handling on pre-R6 cores - HW - Revert "Remove intermediate IRQ forwarder" commits - Implement legacy LTIM Edge/Level Bank Select in Intel 8259 INTC - Improve PCI IRQ routing in VT82C686 / Pegasos II - Basic implementation of VIA AC97 audio playback - Implement 'resume on connection status change' in USB OHCI - UI - Override windowDidResignKey - memory - Dump HPA and access type in HMP 'info ramblock' # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmQHzH8ACgkQ4+MsLN6t # wN4RbxAAtbsbJKHikHevCiE9Fi0E4HHI4su00m3anImogfU3CKIHA7WHgeUVCdVH # aLoFKjvE3d45FA4YwMs13wIo89tv6btn1y8C9iy+yjktdABPUr8OJphuaDxU+yNf # XhPm4WsS0tEg5KzzTHF7qotJGw7Zd0Aca8oezFVBSL8b73lqiJiWBEouFTK9j5Oi # s1uvAOPG3oxSlT7IIbnLRIEff4hi5FZh+LxRDgE3ChcOyY2W/DhrpdVIazv9Cpki # facQ0ozMG4uuZ+HvviuTkK1vLX1+BcS0P1fnDPkXEPAxqx9jdqsMqWHbbnseQPN3 # xcVhw+GOZ67x8qAWIBKDG7nfChbcXgJ2sHxQmvb2XlxnOYw1oO5aRlrnn7ZPEWYA # NbqUHB8G88wDcrms+Y+xCfO8idnr7Kzf4/1R1J1+5yEjg8Y1wu4t0asqZvhXA2HL # F1yhHDCRY8w9pLYmPFGBrINBCoosiDn61g+JTngPffq1zJttmWjSLe9BYOF8Kiw+ # 4YjkCx43wK6RLTZNhU8g7iuqoYbHCQcXx5ZnGEadk+UJcfGrLnOrQbtAhvysS2wo # msyum0FNWhnx/IZ6bmhmbFC8F/hASgyiV9CDwU2oOZ2oAkRiFXYBfXruUAt+6uLT # UnAihAEsyUjyg5YNb4r8ZNkdeCPN6p3s2xY8OHphqu717K6uJXw= # =D/0W # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Mar 2023 23:45:03 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'mips-misc-20230308' of https://github.com/philmd/qemu: log: Remove unneeded new line memory: Dump HPA and access type of ramblocks ui/cocoa: Override windowDidResignKey hw/usb/ohci: Implement resume on connection status change hw/audio/via-ac97: Basic implementation of audio playback hw/usb/vt82c686-uhci-pci: Use PCI IRQ routing hw/ppc/pegasos2: Fix PCI interrupt routing hw/isa/vt82c686: Implement PCI IRQ routing hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select hw/display/sm501: Add debug property to control pixman usage Revert "hw/isa/vt82c686: Remove intermediate IRQ forwarder" Revert "hw/isa/i82378: Remove intermediate IRQ forwarder" hw/mips/itu: Pass SAAR using QOM link property hw/mips: Declare all length properties as unsigned target/mips: Set correct CP0.Config[4, 5] values for M14K(c) target/mips: Implement CP0.Config7.WII bit support target/mips: Fix SWM32 handling for microMIPS target/mips: Fix JALS32/J32 instruction handling for microMIPS target/mips: Replace [g_]assert(0) -> g_assert_not_reached() docs/system: Remove "mips" board from target-mips.rst Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-08hw/usb/ohci: Implement resume on connection status changeBALATON Zoltan1-6/+17
If certain bit is set remote wake up should change state from suspended to resume and generate interrupt. There was a todo comment for this, implement that by moving existing resume logic to a function and call that. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <35c4d4ccf2f73e6a87cdbd28fb6a1b33de72ed74.1676916640.git.balaton@eik.bme.hu> [PMD: Have ohci_resume() return a boolean] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-03-08hw/audio/via-ac97: Basic implementation of audio playbackBALATON Zoltan4-7/+457
Add basic implementation of the AC'97 sound part used in VIA south bridge chips. Not all features of the device is emulated, only one playback channel is supported for now but this is enough to get sound output from some guests using this device on pegasos2. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Volker Rümelin <vr_qemu@t-online.de> Tested-by: Rene Engel <ReneEngel80@emailn.de> Message-Id: <63b99410895312f40e7be479f581da0805e605a1.1678188711.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-03-08hw/usb/vt82c686-uhci-pci: Use PCI IRQ routingBernhard Beschow1-12/+0
According to the PCI specification, PCI_INTERRUPT_LINE shall have no effect on hardware operations. Now that the VIA south bridges implement the internal PCI interrupt router let's be more conformant to the PCI specification. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Rene Engel <ReneEngel80@emailn.de> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <9fb86a74d16db65e3aafbb154238d55e123053eb.1678188711.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-03-08hw/ppc/pegasos2: Fix PCI interrupt routingBALATON Zoltan2-5/+25
According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv64361 north bridge and the PINT pins of the VT8231 south bridge so guests can get interrupts from either of these. So far we only had the MV64361 connections which worked for on board devices but for additional PCI devices (such as network or sound card added with -device) guest OSes expect interrupt from the ISA IRQ 9 where the firmware routes these PCI interrupts in VT8231 ISA bridge. After the previous patches we can now model this and also remove the board specific connection from mv64361. Also configure routing of these lines when using Virtual Open Firmware to match board firmware for guests that expect this. This fixes PCI interrupts on pegasos2 under Linux, MorphOS and AmigaOS. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Message-Id: <520ff9e6eeef600ee14a4116c0c7b11940cc499c.1678188711.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-03-08hw/isa/vt82c686: Implement PCI IRQ routingBALATON Zoltan1-0/+42
The real VIA south bridges implement a PCI IRQ router which is configured by the BIOS or the OS. In order to respect these configurations, QEMU needs to implement it as well. The real chip may allow routing IRQs from internal functions independently of PCI interrupts but since guests usually configute it to a single shared interrupt we don't model that here for simplicity. Note: The implementation was taken from piix4_set_irq() in hw/isa/piix4. Suggested-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Message-Id: <fbb016c7d0e19093335c237e15f5f6c62c4393b4.1678188711.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-03-08hw/intc/i8259: Implement legacy LTIM Edge/Level Bank SelectDavid Woodhouse2-7/+27
Back in the mists of time, before EISA came along and required per-pin level control in the ELCR register, the i8259 had a single chip-wide level-mode control in bit 3 of ICW1. Even in the PIIX3 datasheet from 1996 this is documented as 'This bit is disabled', but apparently MorphOS is using it in the version of the i8259 which is in the Pegasos2 board as part of the VT8231 chipset. It's easy enough to implement, and I think it's harmless enough to do so unconditionally. Signed-off-by: David Woodhouse <dwmw2@infradead.org> [balaton: updated commit message as asked by author] Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <3f09b2dd109d19851d786047ad5c2ff459c90cd7.1678188711.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-03-08hw/display/sm501: Add debug property to control pixman usageBALATON Zoltan1-3/+15
Add a property to allow disabling pixman and always use the fallbacks for different operations which is useful for testing different drawing methods or debugging pixman related issues. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Rene Engel <ReneEngel80@emailn.de> Message-Id: <61768ffaefa71b65a657d1365823bd43c7ee9354.1678188711.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-03-08Revert "hw/isa/vt82c686: Remove intermediate IRQ forwarder"BALATON Zoltan1-1/+9
To be 'usable', QDev objects (which are QOM objects) must be 1/ initialized (at this point their properties can be modified), then 2/ realized (properties are consumed). Some devices (objects) might depend on other devices. When creating the 'QOM composition tree', parent objects can't be 'realized' until all their children are. We might also have circular dependencies. A common circular dependency occurs with IRQs. Device (A) has an output IRQ wired to device (B), and device (B) has one to device (A). When (A) is realized and connects its IRQ to an unrealized (B), the IRQ handler on (B) is not yet created. QEMU pass IRQ between objects as pointer. When (A) poll (B)'s IRQ, it is NULL. Later (B) is realized and its IRQ pointers are populated, but (A) keeps a reference to a NULL pointer. A common pattern to bypass this circular limitation is to use 'proxy' objects. Proxy (P) is created (and realized) before (A) and (B). Then (A) and (B) can be created in different order, it doesn't matter: (P) pointers are already populated. Commit bb98e0f59cde ("hw/isa/vt82c686: Remove intermediate IRQ forwarder") neglected the QOM/QDev circular dependency issue, and removed the 'proxy' between the southbridge, its PCI functions and the interrupt controller, resulting in PCI functions wiring output IRQs to 'NULL', leading to guest failures (IRQ never delivered) [1] [2]. Since we are entering feature freeze, it is safer to revert the offending patch until we figure a way to strengthen our APIs. [1] https://lore.kernel.org/qemu-devel/928a8552-ab62-9e6c-a492-d6453e338b9d@redhat.com/ [2] https://lore.kernel.org/qemu-devel/cover.1677628524.git.balaton@eik.bme.hu/ Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <cdfb3c5a42e505450f6803124f27856434c5b298.1677628524.git.balaton@eik.bme.hu> [PMD: Reworded description] Inspired-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-03-08Revert "hw/isa/i82378: Remove intermediate IRQ forwarder"Philippe Mathieu-Daudé1-1/+9
To be 'usable', QDev objects (which are QOM objects) must be 1/ initialized (at this point their properties can be modified), then 2/ realized (properties are consumed). Some devices (objects) might depend on other devices. When creating the 'QOM composition tree', parent objects can't be 'realized' until all their children are. We might also have circular dependencies. A common circular dependency occurs with IRQs. Device (A) has an output IRQ wired to device (B), and device (B) has one to device (A). When (A) is realized and connects its IRQ to an unrealized (B), the IRQ handler on (B) is not yet created. QEMU pass IRQ between objects as pointer. When (A) poll (B)'s IRQ, it is NULL. Later (B) is realized and its IRQ pointers are populated, but (A) keeps a reference to a NULL pointer. A common pattern to bypass this circular limitation is to use 'proxy' objects. Proxy (P) is created (and realized) before (A) and (B). Then (A) and (B) can be created in different order, it doesn't matter: (P) pointers are already populated. Commit cef2e7148e ("hw/isa/i82378: Remove intermediate IRQ forwarder") neglected the QOM/QDev circular dependency issue, and removed the 'proxy' between the southbridge, its PCI functions and the interrupt controller, resulting in PCI functions wiring output IRQs to 'NULL', leading to guest failures (IRQ never delivered) [1] [2]. Since we are entering feature freeze, it is safer to revert the offending patch until we figure a way to strengthen our APIs. [1] https://lore.kernel.org/qemu-devel/928a8552-ab62-9e6c-a492-d6453e338b9d@redhat.com/ [2] https://lore.kernel.org/qemu-devel/cover.1677628524.git.balaton@eik.bme.hu/ This reverts commit cef2e7148e32d61338de0220619d308bf42af770. Reported-by: Thomas Huth <thuth@redhat.com> Inspired-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-03-08hw/mips/itu: Pass SAAR using QOM link propertyPhilippe Mathieu-Daudé2-25/+24
QOM objects shouldn't access each other internals fields except using the QOM API. mips_cps_realize() instantiates a TYPE_MIPS_ITU object, and directly sets the 'saar' pointer: if (saar_present) { s->itu.saar = &env->CP0_SAAR; } In order to avoid that, pass the MIPS_CPU object via a QOM link property, and set the 'saar' pointer in mips_itu_realize(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20230203113650.78146-10-philmd@linaro.org>
2023-03-08hw/mips: Declare all length properties as unsignedPhilippe Mathieu-Daudé6-13/+13
Some length properties are signed, other unsigned: hw/mips/cps.c:183: DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), hw/mips/cps.c:184: DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), hw/misc/mips_cmgcr.c:215: DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1), hw/misc/mips_cpc.c:167: DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1), hw/misc/mips_itu.c:552: DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo, hw/misc/mips_itu.c:554: DEFINE_PROP_INT32("num-semaphores", MIPSITUState, Since negative values are not used (the minimum is '0'), unify by declaring all properties as unsigned. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230203113650.78146-9-philmd@linaro.org>
2023-03-07Merge tag 'for-upstream-mb' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell1-0/+5
* Fix missing memory barriers * Fix comments about memory ordering # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmQHIqoUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroPYBwgArUaS0KGrBM1XmRUUpXnJokmA37n8 # ft477na+XW+p9VYi27B0R01P8j+AkCrAO0Ir1MLG7axjn5KiRMnbf2uBgqasEREv # repJEXsqISoxA6vvAvnehKHAI9zu8b7frRc/30b6EOrrZpn0JKePSNRTyBu2seGO # NFDXPVA2Wom+xXaNSEGt0dmoJ6AzEVIZKhUIwyvUWOC7MXuuIkRWn9/nySUdvEt0 # RIFPPk7JCjnEc32vb4Xnq/Ncsy20tMIM1hlDxMOVNq3brjeSCzS0PPPSjE/X5OtW # Yn5YS0nCyD7wjP2dkXI4I1lUPxUUx6LvMz1aGbJCfyjSX41mNES/agoGgA== # =KEUo # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Mar 2023 11:40:26 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream-mb' of https://gitlab.com/bonzini/qemu: async: clarify usage of barriers in the polling case async: update documentation of the memory barriers physmem: add missing memory barrier qemu-coroutine-lock: add smp_mb__after_rmw() aio-wait: switch to smp_mb__after_rmw() edu: add smp_mb__after_rmw() qemu-thread-win32: cleanup, fix, document QemuEvent qemu-thread-posix: cleanup, fix, document QemuEvent qatomic: add smp_mb__before/after_rmw() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-07hw/arm/aspeed: Modified BMC FRU byte data in yosemitev2Karthikeyan Pasupathi1-5/+5
Modified BMC FRU data in yosemite v2 platform. Tested: Tested and Verified in yosemitev2 platform. Fixes: 34f73a81e6 ("hw/arm/aspeed: Adding new machine Yosemitev2 in QEMU") Signed-off-by: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20230307104833.3587947-1-pkarthikeyan1509@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-03-07hw/arm/aspeed: Added TMP421 type sensor's support in tiogapassKarthikeyan Pasupathi1-0/+4
Added TMP421 type sensor support in tiogapass platform. Tested: Tested and verified in tiogapass platform. Signed-off-by: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20230307103334.3586755-1-pkarthikeyan1509@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-03-07hw/arm/aspeed: Added TMP421 type sensor's support in yosemitev2Karthikeyan Pasupathi1-0/+5
Added TMP421 type support in yosemite v2 platform. Tested: Tested and verified in yosemite V2 platform. Signed-off-by: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20230307095239.3583613-1-pkarthikeyan1509@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-03-07pflash: Fix blk_pread_nonzeroes()Kevin Wolf1-2/+1
Commit a4b15a8b introduced a new function blk_pread_nonzeroes(). Instead of reading directly from the root node of the BlockBackend, it reads from its 'file' child node. This can happen to mostly work for raw images (as long as the 'raw' format driver is in use, but not actually doing anything), but it breaks everything else. Fix it to read from the root node instead. Fixes: a4b15a8b9ef25b44fa92a4825312622600c1f37c Reported-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20230307140230.59158-1-kwolf@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-03-07m25p80: Improve error when the backend file size does not match the deviceCédric Le Goater1-2/+2
Currently, when a block backend is attached to a m25p80 device and the associated file size does not match the flash model, QEMU complains with the error message "failed to read the initial flash content". This is confusing for the user. Instead, use helper blk_check_size_and_read_all() introduced by commit 06f1521795 ("pflash: Require backend size to match device, improve errors"). Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221115151000.2080833-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-03-07Merge tag 'pull-riscv-to-apply-20230306' of ↵Peter Maydell7-21/+493
https://gitlab.com/palmer-dabbelt/qemu into staging Sixth RISC-V PR for 8.0 * Support for the Zicbiom, ZCicboz, and Zicbop extensions. * OpenSBI has been updated to version 1.2, see <https://github.com/riscv-software-src/opensbi/releases/tag/v1.2> for the release notes. * Support for setting the virtual address width (ie, sv39/sv48/sv57) on the command line. * Support for ACPI on RISC-V. # -----BEGIN PGP SIGNATURE----- # # iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmQGYGgTHHBhbG1lckBk # YWJiZWx0LmNvbQAKCRAuExnzX7sYidmyEAC6FEMbbFM5D++qR6w6xM6hXgzcrev6 # s1kyRRNVa45uSA78ti/Zi0hsDLNf7ZsNPndF0OIkkO5iAE0OVm3LU7tV1TqKcT82 # Dd9VXxe93zEmfnuJazHrMa54SXPhhnNdWHtKlZ6vBfZpbxgx0FFs50xkCsrM5LQZ # hYHxQUqPWQTvF2MdDHrxCuLcdKl+Wg3ysCcgRh2d049KUBrIu6vNaHC2+AGRjCbj # BkrGCkB82fTmVJjzAcVWQxLoAV12pCbJS4og1GtP8hA7WevtB39tbPin9siBKRZp # QBeiIsg0nebkpmZGrb+xWVwlIBNe9yYwJa0KmveQk8v7L5RIzjM1mtDL91VrVljC # KC2tfT570m0Iq2NoFMb3wd/kESHFzVDM/g+XYqRd4KSoiCNP/RbqYNQBwbMc31Tr # E27xfA1D8w2vem0Rk20x3KgPf1Z5OmGXjq6YObTpnAzG8cZlA37qKBP+ortt5aHX # GZSg3CAwknHHVajd4aaegkPsHxm1tRvoTfh38MwkPSNxaA9GD0nz0k9xaYDmeZ2L # olfanNsaQEwcVUId31+7sAENg1TZU0fnj879/nxkMUCazVTdL8/mz+IoTTx0QCST # 3+9ATWcyJUlmjbDKIs7kr1L+wJdvvHEJggPAbbPI8ekpXaLZvUYOT6ObzYKNAmwY # wELQBn8QKXcLVA== # =5gAt # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 Mar 2023 21:51:36 GMT # gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 # Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889 * tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt/qemu: (22 commits) MAINTAINERS: Add entry for RISC-V ACPI hw/riscv/virt.c: Initialize the ACPI tables hw/riscv/virt: virt-acpi-build.c: Add RHCT Table hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT hw/riscv/virt: Enable basic ACPI infrastructure hw/riscv/virt: Add memmap pointer to RiscVVirtState hw/riscv/virt: Add a switch to disable ACPI hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields riscv: Correctly set the device-tree entry 'mmu-type' riscv: Introduce satp mode hw capabilities riscv: Allow user to set the satp mode riscv: Change type of valid_vm_1_10_[32|64] to bool riscv: Pass Object to register_cpu_props instead of DeviceState roms/opensbi: Upgrade from v1.1 to v1.2 gitlab/opensbi: Move to docker:stable hw: intc: Use cpu_by_arch_id to fetch CPU state target/riscv: cpu: Implement get_arch_id callback disas/riscv Fix ctzw disassemble hw/riscv/virt.c: add cbo[mz]-block-size fdt properties target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-07edu: add smp_mb__after_rmw()Paolo Bonzini1-0/+5
Ensure ordering between clearing the COMPUTING flag and checking IRQFACT, and between setting the IRQFACT flag and checking COMPUTING. This ensures that no wakeups are lost. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-03-07Merge tag 'pull-target-arm-20230306' of ↵Peter Maydell4-6/+146
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * allwinner-h3: Fix I2C controller model for Sun6i SoCs * allwinner-h3: Add missing i2c controllers * Expose M-profile system registers to gdbstub * Expose pauth information to gdbstub * Support direct boot for Linux/arm64 EFI zboot images * Fix incorrect stage 2 MMU setup validation # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmQGB+wZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3gdQEACVfgbs77mxbOb6u8yWHKGZ # tVnQr9KZMv2lmwt5H3ROJPXznchrIIAwdMeRgKnbI+lC5jTq9L+Q8RJch3t/EbAd # f0VMyiPe3DzCbCrAR9cW6EWzbYnEVo3Ioj4k7qjxK6u1BIKhXz99DLYd1KRdTxnx # BAYmcl857Uir1q2FrBVMZ/ItCLbk4ejn+YaDIawNue2/s1oGa+we473x9rosCFvp # L9bzT3R46e0o+Mfkn1OYRmgCmURTalWPpWAxyOUFR9YbrzXleLgAKEB3o3PPcvls # u26uxztyRMqje1q06VjUzwaLw7zN9XPhmir+NXX7KXp2/x9PZjApOpPtt0kl+6qe # FbByKfl24O9w/OKewsJw+udCBYdYrRPm6tWv2D71iAwjBUzBJgNGe5VPRdPFtPDn # uSRO65o34w1nPzRpAheUciZueiabYrVmIgVltFxj0JlrKGfgiYHPLVyU0Uu0K/A7 # F2kUEQIzIcWdo+c8SlvlWOEA2ojVd/KoLVLgndqr40Tk5pbc65TRS08kkVVl4cMT # jUGscl7Dyxe+yo8+nHdycAJpnKYDllJOh2JbGv3r2FqCy5FMuIqW4hHeuUxwpE+O # nxm7lzjnaVHSAFHdzhk9x4E4uH/GTcdWzX1EsmpgGqe5oejLJOrCINb+Dj44+Y8h # 8aGRvE7kxMs11upxc7BcAw== # =KIMt # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 Mar 2023 15:34:04 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20230306' of https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits) hw: arm: allwinner-h3: Fix and complete H3 i2c devices hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs hw: arm: Support direct boot for Linux/arm64 EFI zboot images target/arm: Rewrite check_s2_mmu_setup target/arm: Diagnose incorrect usage of arm_is_secure subroutines target/arm: Stub arm_hcr_el2_eff for m-profile target/arm: Handle m-profile in arm_is_secure target/arm: Implement gdbstub m-profile systemreg and secext target/arm: Export arm_v7m_get_sp_ptr target/arm: Export arm_v7m_mrs_control target/arm: Implement gdbstub pauth extension target/arm: Create pauth_ptr_mask target/arm: Simplify iteration over bit widths target/arm: Add name argument to output_vector_union_type target/arm: Fix svep width in arm_gen_dynamic_svereg_xml target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml target/arm: Split out output_vector_union_type target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c target/arm: Unexport arm_gen_dynamic_sysreg_xml ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-07Merge tag 'nvme-next-pull-request' of https://gitlab.com/birkelund/qemu into ↵Peter Maydell5-14/+1122
staging hw/nvme updates * basic support for directives * simple support for endurance groups * emulation of flexible data placement (tp4146) # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmQF+doACgkQTeGvMW1P # DenIEgf+MLsRQ3kKUmsgVNnPuR69M0COfyaz0AnfX6YEIL9ukFJQPsmASfPmHof5 # tCYIFyKEpZt/givmzSI1jdpm0uX2MRwLGLYRdNhEPVjo+TfGda15x7DgpBEduqjq # mChUS2wrmgP9TZne+kTAU28pUpU7hcfrt1RkDOO86W8oJmpBeIyGe6vikVhQppKW # fAIKvhNfN3p5Kxq1fhE6I5YzKd2vvKtBvPpZp2uFe6LHXEcVV/FPcTx3Ph+um/o6 # ScmmxowT4Wqk4EgXh1ohephlxB89aWgwLNHLHcfte6UCU9x4eSmTC2T3pf7piBaE # pGLpzPoYk6BAurwrMuxCxYgStl6SzQ== # =CNSk # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 Mar 2023 14:34:02 GMT # gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9 # gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [full] # gpg: aka "Klaus Jensen <k.jensen@samsung.com>" [full] # Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838 # Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9 * tag 'nvme-next-pull-request' of https://gitlab.com/birkelund/qemu: hw/nvme: flexible data placement emulation hw/nvme: basic directives support hw/nvme: add basic endurance group support hw/nvme: store a pointer to the NvmeSubsystem in the NvmeNamespace hw/nvme: move adjustment of data_units{read,written} Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06hw/riscv/virt.c: Initialize the ACPI tablesSunil V L1-0/+4
Initialize the ACPI tables if the acpi option is not disabled. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-8-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06hw/riscv/virt: virt-acpi-build.c: Add RHCT TableSunil V L1-0/+78
RISC-V ACPI platforms need to provide RISC-V Hart Capabilities Table (RHCT). Add this to the ACPI tables. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-7-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADTSunil V L1-0/+34
Add Multiple APIC Description Table (MADT) with the RINTC structure for each cpu. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-6-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06hw/riscv/virt: Enable basic ACPI infrastructureSunil V L3-0/+306
Add basic ACPI infrastructure for RISC-V with below tables. 1) DSDT with below basic objects - CPUs - fw_cfg 2) FADT revision 6 with HW_REDUCED flag 3) XSDT 4) RSDP Add this functionality in a new file virt-acpi-build.c and enable building this infrastructure. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-5-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06hw/riscv/virt: Add memmap pointer to RiscVVirtStateSunil V L1-0/+2
memmap needs to be exported outside of virt.c so that modules like acpi can use it. Hence, add a pointer field in RiscVVirtState structure and initialize it with the memorymap. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-4-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06hw/riscv/virt: Add a switch to disable ACPISunil V L1-0/+29
ACPI will be enabled by default. Add a switch to turn off for testing and debug purposes. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-3-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fieldsSunil V L1-0/+5
ACPI needs OEM_ID and OEM_TABLE_ID for the machine. Add these fields in the RISCVVirtState structure and initialize with default values. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-2-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06riscv: Correctly set the device-tree entry 'mmu-type'Alexandre Ghiti1-8/+11
The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230303131252.892893-6-alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06hw: arm: allwinner-h3: Fix and complete H3 i2c devicesqianfan Zhao1-4/+25
Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi. The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear control register's INT_FLAG bit. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06hw/nvme: flexible data placement emulationJesper Devantier5-7/+1014
Add emulation of TP4146 ("Flexible Data Placement"). Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Jesper Devantier <j.devantier@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2023-03-06hw/nvme: basic directives supportGollu Appalanaidu2-1/+41
Add support for the Directive Send and Recv commands and the Identify directive. Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2023-03-06hw/nvme: add basic endurance group supportKlaus Jensen3-1/+58
Add the mandatory Endurance Group identify data structures and log pages. For now, all namespaces in a subsystem belongs to a single Endurance Group. Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2023-03-06hw/nvme: store a pointer to the NvmeSubsystem in the NvmeNamespaceNiklas Cassel2-0/+2
Each NvmeNamespace can be used by serveral controllers, but a NvmeNamespace can at most belong to a single NvmeSubsystem. Store a pointer to the NvmeSubsystem, if the namespace was realized with a NvmeSubsystem. Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2023-03-06hw/nvme: move adjustment of data_units{read,written}Joel Granados1-6/+8
Move the rounding of bytes read/written into nvme_smart_log which reports in units of 512 bytes, rounded up in thousands. This is in preparation for adding the Endurance Group Information log page which reports in units of billions, rounded up. Reviewed-by: Keith Busch <kbusch@kernel.org> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Joel Granados <j.granados@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2023-03-06hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCsqianfan Zhao1-2/+24
TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect) register on SUN6i based SoCs, we should lower interrupt when the guest set this bit. The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no device connected on the i2c bus, next is the trace log: allwinner_i2c_write write CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN allwinner_i2c_write write CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN allwinner_i2c_read read CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN allwinner_i2c_read read STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE ... Fix it. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06hw: arm: Support direct boot for Linux/arm64 EFI zboot imagesArd Biesheuvel2-0/+97
Fedora 39 will ship its arm64 kernels in the new generic EFI zboot format, using gzip compression for the payload. For doing EFI boot in QEMU, this is completely transparent, as the firmware or bootloader will take care of this. However, for direct kernel boot without firmware, we will lose the ability to boot such distro kernels unless we deal with the new format directly. EFI zboot images contain metadata in the header regarding the placement of the compressed payload inside the image, and the type of compression used. This means we can wire up the existing gzip support without too much hassle, by parsing the header and grabbing the payload from inside the loaded zboot image. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Message-id: 20230303160109.3626966-1-ardb@kernel.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked comment formatting, fixed checkpatch nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06hw/xen/xen_pt: fix uninitialized variableMarek Marczykowski-Górecki1-1/+1
xen_pt_config_reg_init() reads only that many bytes as the size of the register that is being initialized. It uses xen_host_pci_get_{byte,word,long} and casts its last argument to expected pointer type. This means for smaller registers higher bits of 'val' are not initialized. Then, the function fails if any of those higher bits are set. Fix this by initializing 'val' with zero. Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-Id: <20230127050815.4155276-1-marmarek@invisiblethingslab.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2023-03-06xen/pt: reserve PCI slot 2 for Intel igd-passthruChuck Zmudzinski4-11/+78
Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus, as noted in docs/igd-assign.txt in the Qemu source code. Currently, when the xl toolstack is used to configure a Xen HVM guest with Intel IGD passthrough to the guest with the Qemu upstream device model, a Qemu emulated PCI device will occupy slot 2 and the Intel IGD will occupy a different slot. This problem often prevents the guest from booting. The only available workarounds are not good: Configure Xen HVM guests to use the old and no longer maintained Qemu traditional device model available from xenbits.xen.org which does reserve slot 2 for the Intel IGD or use the "pc" machine type instead of the "xenfv" machine type and add the xen platform device at slot 3 using a command line option instead of patching qemu to fix the "xenfv" machine type directly. The second workaround causes some degredation in startup performance such as a longer boot time and reduced resolution of the grub menu that is displayed on the monitor. This patch avoids that reduced startup performance when using the Qemu upstream device model for Xen HVM guests configured with the igd-passthru=on option. To implement this feature in the Qemu upstream device model for Xen HVM guests, introduce the following new functions, types, and macros: * XEN_PT_DEVICE_CLASS declaration, based on the existing TYPE_XEN_PT_DEVICE * XEN_PT_DEVICE_GET_CLASS macro helper function for XEN_PT_DEVICE_CLASS * typedef XenPTQdevRealize function pointer * XEN_PCI_IGD_SLOT_MASK, the value of slot_reserved_mask to reserve slot 2 * xen_igd_reserve_slot and xen_igd_clear_slot functions Michael Tsirkin: * Introduce XEN_PCI_IGD_DOMAIN, XEN_PCI_IGD_BUS, XEN_PCI_IGD_DEV, and XEN_PCI_IGD_FN - use them to compute the value of XEN_PCI_IGD_SLOT_MASK The new xen_igd_reserve_slot function uses the existing slot_reserved_mask member of PCIBus to reserve PCI slot 2 for Xen HVM guests configured using the xl toolstack with the gfx_passthru option enabled, which sets the igd-passthru=on option to Qemu for the Xen HVM machine type. The new xen_igd_reserve_slot function also needs to be implemented in hw/xen/xen_pt_stub.c to prevent FTBFS during the link stage for the case when Qemu is configured with --enable-xen and --disable-xen-pci-passthrough, in which case it does nothing. The new xen_igd_clear_slot function overrides qdev->realize of the parent PCI device class to enable the Intel IGD to occupy slot 2 on the PCI bus since slot 2 was reserved by xen_igd_reserve_slot when the PCI bus was created in hw/i386/pc_piix.c for the case when igd-passthru=on. Move the call to xen_host_pci_device_get, and the associated error handling, from xen_pt_realize to the new xen_igd_clear_slot function to initialize the device class and vendor values which enables the checks for the Intel IGD to succeed. The verification that the host device is an Intel IGD to be passed through is done by checking the domain, bus, slot, and function values as well as by checking that gfx_passthru is enabled, the device class is VGA, and the device vendor in Intel. Signed-off-by: Chuck Zmudzinski <brchuckz@aol.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-Id: <b1b4a21fe9a600b1322742dda55a40e9961daa57.1674346505.git.brchuckz@aol.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2023-03-05hw: intc: Use cpu_by_arch_id to fetch CPU stateMayuresh Chitale3-13/+13
Qemu_get_cpu uses the logical CPU id assigned during init to fetch the CPU state. However APLIC, IMSIC and ACLINT contain registers and states which are specific to physical hart Ids. The hart Ids in any given system might be sparse and hence calls to qemu_get_cpu need to be replaced by cpu_by_arch_id which performs lookup based on the sparse physical hart IDs. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230303065055.915652-3-mchitale@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05hw/riscv/virt.c: add cbo[mz]-block-size fdt propertiesAnup Patel1-0/+11
The cbom-block-size fdt property property is used to inform the OS about the blocksize in bytes for the Zicbom cache operations. Linux documents it in Documentation/devicetree/bindings/riscv/cpus.yaml as: riscv,cbom-block-size: $ref: /schemas/types.yaml#/definitions/uint32 description: The blocksize in bytes for the Zicbom cache operations. cboz-block-size has the same role but for the Zicboz extension, i.e. informs the size in bytes for Zicboz cache operations. Linux support for it is under review/approval in [1]. Patch 3 of that series describes cboz-block-size as: riscv,cboz-block-size: $ref: /schemas/types.yaml#/definitions/uint32 description: The blocksize in bytes for the Zicboz cache operations. [1] https://lore.kernel.org/all/20230224162631.405473-1-ajones@ventanamicro.com/ Cc: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Message-ID: <20230302091406.407824-2-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-04Merge tag 'pull-ppc-20230303' of https://gitlab.com/danielhb/qemu into stagingPeter Maydell3-70/+72
ppc patch queue for 2023-03-03: This queue includes a stub implementation for the dcblc instruction to avoid an illegal instrunction exception when using u-boot with mpc85xx. It also includes a PHB fix with user-created pnv-phb devices and Skiboot. # -----BEGIN PGP SIGNATURE----- # # iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZAJllhYcZGFuaWVsaGI0 # MTNAZ21haWwuY29tAAoJEDzZypbeAzFk02YA/2YnJl0aRw6hgiayI2rLbcwQcVfp # oGAhh4QmqFL2UJw2AQDra0kh9sxBSEcqhltNnOa08tBnHPts3W/A8nmFtCd4Cw== # =VRNM # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Mar 2023 21:24:38 GMT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20230303' of https://gitlab.com/danielhb/qemu: pnv_phb4_pec: Simplify/align code to parent user-created PHBs pnv_phb4_pec: Move pnv_phb4_get_pec() to rightful file pnv_phb4_pec: Only export existing PHBs to the device tree pnv_phb4_pec: Keep track of instantiated PHBs target/ppc/translate: Add dummy implementation for dcblc instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-03pnv_phb4_pec: Simplify/align code to parent user-created PHBsFrederic Barrat3-23/+20
When instantiating a user-created PHB on P9/P10, we don't really have a reason any more to go through an indirection in pnv_chip_add_phb() in pnv.c, we can go straight to the right function in pnv_phb4_pec.c. That way, default PHBs and user-created PHBs are all handled in the same file. This patch also renames pnv_phb4_get_pec() to pnv_pec_add_phb() to better reflect that it "hooks" a PHB to a PEC. For P8, the PHBs are parented to the chip directly, so it makes sense to keep calling pnv_chip_add_phb() in pnv.c, to also be consistent with where default PHBs are handled. The only change here is that, since that function is now only used for P8, we can refine the return type. So overall, the PnvPHB front-end now has a pnv_phb_user_get_parent() function which handles the parenting of the user-created PHBs by calling the right function in the right file based on the processor version. It's also easily extensible if we ever need to support a different parent object. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20230302163715.129635-5-fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-03-03pnv_phb4_pec: Move pnv_phb4_get_pec() to rightful fileFrederic Barrat2-43/+41
The function pnv_phb4_get_pec() exposes some internals of the PEC and PHB logic, yet it was in the higher level hw/ppc/pnv.c file for historical reasons: P8 implements the PHBs from pnv.c directly, but on P9/P10, it's done through the CEC model, which has its own file. So move pnv_phb4_get_pec() to hw/pci-host/pnv_phb4_pec.c, where it fits naturally. While at it, replace the PnvPHB4 parameter by the PnvPHB front-end, since it has all the information needed and simplify it a bit. No functional changes. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20230302163715.129635-4-fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-03-03pnv_phb4_pec: Only export existing PHBs to the device treeFrederic Barrat1-2/+6
So far, we were always exporting all possible PHBs to the device tree. It works well when using the default config but it potentially adds non-existing devices when using '-nodefaults' and user-created PHBs, causing the firmware (skiboot) to report errors when probing those PHBs. This patch only exports PHBs which have been realized to the device tree. Fixes: d786be3fe746 ("ppc/pnv: enable user created pnv-phb for powernv9") Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20230302163715.129635-3-fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-03-03pnv_phb4_pec: Keep track of instantiated PHBsFrederic Barrat2-5/+8
Add an array on the PEC object to keep track of the PHBs which are instantiated. The array can be sparsely populated when using user-created PHBs. It will be useful for the next patch to only export instantiated PHBs in the device tree. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20230302163715.129635-2-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-03-03Merge tag 'pull-aspeed-20230302' of https://github.com/legoater/qemu into ↵Peter Maydell12-77/+400
staging aspeed queue: * fix for the Aspeed I2C slave mode * a new I2C echo device from Klaus and its associated test in avocado. * initial SoC cleanups to allow the use of block devices instead of drives on the command line. * new facebook machines and eeprom fixes for the Fuji * readline fix # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmQAnrQACgkQUaNDx8/7 # 7KGIvQ//Te2eSxlZNxAXHb3HSVFRaBW+2EkJzNlalX75olFSzCLe8BnAHK5xPlYv # JjU0aPjWaPohPLdbNbAsJY2B8AwMGbUTjSv+ORRWF6s97LTVD9WcAYHgOTCz6d2X # ZrArJ5msEQAFEySOLmBqTcuyW3t4w8XeII+B09HZIS8Gn3F9kX5+4JCw9E4sX8fS # n9ayclMmrXCPbkGA4bfwJp3KI1Tc/WXNRyG0AmPEmepid7ECr5tVvQoXRMF1Sy/D # 10qbHEcmQXvZDy85M2ED1niOac4oU+EY8Wvjzkgc36uXcjqf0jIUfw56cwGSNVkW # MhPXSMiH4tEjgxmtzld3LeA6TGfrFcCvRXYiCuYWHjBS3gptlqY6Q0580vxoQVXL # lTYui57LB1YStNLcLG9toP0d4/fRfeqEx7ddCQKlopnW/K392eoJo0aYoVGVJhIC # 3QhN525EFUwMm4FDpdSW29Gfbk/ytpf0u4hQ6JPeBl8psirRKqCGuwr5NOnPYTaN # yErlsq2eL83t9kLo+2YIqgWic85wNP3kqAjIaE6lminqX7sWFH3V1g9HqUQZVG1g # msatZMiCCvwSFuz3DPkSfnuhqwaHuhvCATZloCtguCmnbUK9qUVVzvodKw62sZrd # GdS2XvRNyoOwezz0tDEvPipyZ7RpcaatryHNuzGwRsE5Lvr73dg= # =ExnJ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 02 Mar 2023 13:03:48 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20230302' of https://github.com/legoater/qemu: aspeed/smc: Replace SysBus IRQs with GPIO lines aspeed: Add a boot_rom overlap region in the SoC spi_boot container aspeed: Introduce a spi_boot region under the SoC aspeed/fuji : correct the eeprom size hw/at24c : modify at24c to support 1 byte address mode hw/arm/aspeed: Adding new machine Tiogapass in QEMU hw/arm/aspeed: Adding new machine Yosemitev2 in QEMU tests/avocado/machine_aspeed.py: Add an I2C slave test hw/misc: add a toy i2c echo device hw/i2c: only schedule pending master when bus is idle readline: fix hmp completion issue Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-03Merge tag 'pull-loongarch-20230303' of https://gitlab.com/gaosong/qemu into ↵Peter Maydell2-5/+18
staging pull-loongarch-20230303 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZAFb5wAKCRBAov/yOSY+ # 35hmA/sHIGXU5zQV6p6DBILFGEE6x91sPtV8WKY3zujVY0hsfD4SF6bKTaKJYisZ # EztZZ5/EunQcu/vfgO46YtYysEWzrzGiinbZ5lAjxk6sdlBYlfcTQLAQEEW3zPbP # qB3SiiGmGQ0iYFHIlkyi1tCF5OEmqqQKrHYrNVk6cGBoJle2PA== # =giPH # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Mar 2023 02:31:03 GMT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20230303' of https://gitlab.com/gaosong/qemu: hw/loongarch/virt: add system_powerdown hmp command support target/loongarch: Implement Chip Configuraiton Version Register(0x0000) docs/system/loongarch: update loongson3.rst and rename it to virt.rst loongarch: Add smbios command line option. hw/loongarch/virt: rename PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-02-23 02:25:08 +0000