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2023-10-20hw/hppa: Export machine name, BTLBs, power-button address via fw_cfgHelge Deller1-3/+19
Provide necessary info to SeaBIOS-hppa. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-20pci-host: Wire up new Astro/Elroy PCI bridgeHelge Deller3-0/+6
Allow the Astro source to be built. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-20hw/pci-host: Add Astro system bus adapter found on PA-RISC machinesHelge Deller2-0/+896
The 64-bit PA-RISC machines use a Astro system bus adapter (SBA) with Elroy PCI host chips. Later generation Astro chips were named Pluto, Ike and REO. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-19ui/input: Constify QemuInputHandler structurePhilippe Mathieu-Daudé6-14/+14
Access to QemuInputHandlerState::handler are read-only. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231017131251.43708-1-philmd@linaro.org>
2023-10-19hw/net: Declare link using static DEFINE_PROP_LINK() macroPhilippe Mathieu-Daudé1-5/+2
Declare link statically using DEFINE_PROP_LINK(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231017140150.44995-7-philmd@linaro.org>
2023-10-19hw/dma: Declare link using static DEFINE_PROP_LINK() macroPhilippe Mathieu-Daudé3-18/+8
Declare link statically using DEFINE_PROP_LINK(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231017140150.44995-6-philmd@linaro.org>
2023-10-19hw/scsi/virtio-scsi: Use VIRTIO_SCSI_COMMON() macroPhilippe Mathieu-Daudé1-1/+1
Access QOM parent with the proper QOM VIRTIO_SCSI_COMMON() macro. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231017140150.44995-5-philmd@linaro.org>
2023-10-19hw/display/virtio-gpu: Use VIRTIO_DEVICE() macroPhilippe Mathieu-Daudé1-1/+1
Access QOM parent with the proper QOM VIRTIO_DEVICE() macro. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231017140150.44995-4-philmd@linaro.org>
2023-10-19hw/block/vhost-user-blk: Use DEVICE() / VIRTIO_DEVICE() macrosPhilippe Mathieu-Daudé1-2/+2
Access QOM parent with the proper QOM [VIRTIO_]DEVICE() macros. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231017140150.44995-3-philmd@linaro.org>
2023-10-19hw/virtio/virtio-pmem: Replace impossible check by assertionPhilippe Mathieu-Daudé1-4/+1
The get_memory_region() handler is used when (un)plugging the device, which can only occur *after* it is realized. virtio_pmem_realize() ensure the instance can not be realized without 'memdev'. Remove the superfluous check, replacing it by an assertion. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-Id: <20231017140150.44995-2-philmd@linaro.org>
2023-10-19hw/s390x/css-bridge: Realize sysbus device before accessing itPhilippe Mathieu-Daudé1-4/+3
qbus_new() should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231019071611.98885-10-philmd@linaro.org>
2023-10-19hw/isa: Realize ISA bridge device before accessing itPhilippe Mathieu-Daudé1-2/+9
qbus_new() should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231019071611.98885-9-philmd@linaro.org>
2023-10-19hw/arm/virt: Realize ARM_GICV2M sysbus device before accessing itPhilippe Mathieu-Daudé1-1/+1
sysbus_mmio_map() should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231018141151.87466-8-philmd@linaro.org>
2023-10-19hw/acpi: Realize ACPI_GED sysbus device before accessing itPhilippe Mathieu-Daudé3-4/+3
sysbus_mmio_map() should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231018141151.87466-7-philmd@linaro.org>
2023-10-19hw/pci-host/bonito: Do not use SysBus API to map local MMIO regionPhilippe Mathieu-Daudé1-17/+13
There is no point in exposing an internal MMIO region via SysBus and directly mapping it in the very same device. Just map it without using the SysBus API. Transformation done using the following coccinelle script: @@ expression sbdev; expression index; expression addr; expression subregion; @@ - sysbus_init_mmio(sbdev, subregion); ... when != sbdev - sysbus_mmio_map(sbdev, index, addr); + memory_region_add_subregion(get_system_memory(), addr, subregion); and manually adding the local 'host_mem' variable to avoid multiple calls to get_system_memory(). Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231019071611.98885-6-philmd@linaro.org>
2023-10-19hw/misc/allwinner-dramc: Do not use SysBus API to map local MMIO regionPhilippe Mathieu-Daudé1-7/+6
There is no point in exposing an internal MMIO region via SysBus and directly mapping it in the very same device. Just map it without using the SysBus API. Transformation done using the following coccinelle script: @@ expression sbdev; expression index; expression addr; expression subregion; @@ - sysbus_init_mmio(sbdev, subregion); ... when != sbdev - sysbus_mmio_map(sbdev, index, addr); + memory_region_add_subregion(get_system_memory(), + addr, subregion); @@ expression priority; @@ - sysbus_init_mmio(sbdev, subregion); ... when != sbdev - sysbus_mmio_map_overlap(sbdev, index, addr, priority); + memory_region_add_subregion_overlap(get_system_memory(), + addr, + subregion, priority); Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231019071611.98885-5-philmd@linaro.org>
2023-10-19hw/misc/allwinner-dramc: Move sysbus_mmio_map call from init -> realizePhilippe Mathieu-Daudé1-8/+7
In order to make the next commit trivial, move the sysbus_init_mmio() call in allwinner_r40_dramc_init() just before the corresponding sysbus_mmio_map_overlap() call in allwinner_r40_dramc_realize(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231019071611.98885-4-philmd@linaro.org>
2023-10-19hw/i386/intel_iommu: Do not use SysBus API to map local MMIO regionPhilippe Mathieu-Daudé1-3/+2
There is no point in exposing an internal MMIO region via SysBus and directly mapping it in the very same device. Just map it without using the SysBus API. Transformation done using the following coccinelle script: @@ expression sbdev; expression index; expression addr; expression subregion; @@ - sysbus_init_mmio(sbdev, subregion); ... when != sbdev - sysbus_mmio_map(sbdev, index, addr); + memory_region_add_subregion(get_system_memory(), addr, subregion); Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231018141151.87466-3-philmd@linaro.org>
2023-10-19hw/i386/amd_iommu: Do not use SysBus API to map local MMIO regionPhilippe Mathieu-Daudé1-3/+2
There is no point in exposing an internal MMIO region via SysBus and directly mapping it in the very same device. Just map it without using the SysBus API. Transformation done using the following coccinelle script: @@ expression sbdev; expression index; expression addr; expression subregion; @@ - sysbus_init_mmio(sbdev, subregion); ... when != sbdev - sysbus_mmio_map(sbdev, index, addr); + memory_region_add_subregion(get_system_memory(), addr, subregion); Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231018141151.87466-2-philmd@linaro.org>
2023-10-19hw/audio/pcspk: Inline pcspk_init()Philippe Mathieu-Daudé3-3/+11
pcspk_init() is a legacy init function, inline and remove it. Since the device is realized using &error_fatal, use the same error for setting the "pit" link. Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231019073307.99608-1-philmd@linaro.org>
2023-10-19hw/intc/spapr_xive: Do not use SysBus API to map local MMIO regionPhilippe Mathieu-Daudé1-6/+6
There is no point in exposing an internal MMIO region via SysBus and directly mapping it in the very same device. Just map it without using the SysBus API. Transformation done using the following coccinelle script: @@ expression sbdev; expression index; expression addr; expression subregion; @@ - sysbus_init_mmio(sbdev, subregion); ... when != sbdev - sysbus_mmio_map(sbdev, index, addr); + memory_region_add_subregion(get_system_memory(), addr, subregion); Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20231019131647.19690-8-philmd@linaro.org>
2023-10-19hw/intc/spapr_xive: Move sysbus_init_mmio() calls aroundPhilippe Mathieu-Daudé1-3/+3
In order to make the next commit trivial, move sysbus_init_mmio() calls just before the corresponding sysbus_mmio_map() calls. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20231019131647.19690-7-philmd@linaro.org>
2023-10-19hw/ppc/pnv: Do not use SysBus API to map local MMIO regionPhilippe Mathieu-Daudé1-3/+2
There is no point in exposing an internal MMIO region via SysBus and directly mapping it in the very same device. Just map it without using the SysBus API. Transformation done using the following coccinelle script: @@ expression sbdev; expression index; expression addr; expression subregion; @@ - sysbus_init_mmio(sbdev, subregion); ... when != sbdev - sysbus_mmio_map(sbdev, index, addr); + memory_region_add_subregion(get_system_memory(), addr, subregion); Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20231019131647.19690-6-philmd@linaro.org>
2023-10-19hw/ppc/pnv_xscom: Do not use SysBus API to map local MMIO regionPhilippe Mathieu-Daudé1-3/+1
There is no point in exposing an internal MMIO region via SysBus and directly mapping it in the very same device. Just map it without using the SysBus API. Transformation done using the following coccinelle script: @@ expression sbdev; expression index; expression addr; expression subregion; @@ - sysbus_init_mmio(sbdev, subregion); ... when != sbdev - sysbus_mmio_map(sbdev, index, addr); + memory_region_add_subregion(get_system_memory(), addr, subregion); Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20231019131647.19690-5-philmd@linaro.org>
2023-10-19hw/ppc/pnv_xscom: Move sysbus_mmio_map() call within pnv_xscom_init()Philippe Mathieu-Daudé2-7/+5
In order to make the next commit trivial, move sysbus_init_mmio() calls just before the corresponding sysbus_mmio_map() calls. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20231019131647.19690-4-philmd@linaro.org>
2023-10-19hw/ppc/pnv_xscom: Rename pnv_xscom_realize(Error **) -> pnv_xscom_init()Philippe Mathieu-Daudé2-16/+4
pnv_xscom_realize() is not used to *realize* QDev object, rename it as pnv_xscom_init(). The Error** argument is unused: remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20231019131647.19690-3-philmd@linaro.org>
2023-10-19hw/ppc/spapr_vio: Realize SPAPR_VIO_BRIDGE device before accessing itPhilippe Mathieu-Daudé1-1/+2
qbus_new() should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231019131647.19690-2-philmd@linaro.org>
2023-10-19hw/intc/apic: Use ERRP_GUARD() in apic_common_realize()Philippe Mathieu-Daudé1-0/+4
APICCommonClass::realize() is a DeviceRealize() handler which take an Error** parameter and can fail. Do not proceed further on failure. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <20231003082728.83496-2-philmd@linaro.org>
2023-10-19hw/s390x: Clean up global variable shadowing in quiesce_powerdown_req()Philippe Mathieu-Daudé1-4/+4
Fix: hw/s390x/sclpquiesce.c:90:22: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] QuiesceNotifier *qn = container_of(n, QuiesceNotifier, notifier); ^ hw/s390x/sclpquiesce.c:86:3: note: previous declaration is here } qn; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20231010115048.11856-7-philmd@linaro.org>
2023-10-19hw/pci: Clean up global variable shadowing of address_space_io variablePhilippe Mathieu-Daudé1-16/+9
Fix: hw/pci/pci.c:504:54: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] MemoryRegion *address_space_io, ^ hw/pci/pci.c:533:38: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] MemoryRegion *address_space_io, ^ hw/pci/pci.c:543:40: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] MemoryRegion *address_space_io, ^ hw/pci/pci.c:590:45: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] MemoryRegion *address_space_io, ^ include/exec/address-spaces.h:35:21: note: previous declaration is here extern AddressSpace address_space_io; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231010115048.11856-6-philmd@linaro.org>
2023-10-19hw/acpi/pcihp: Clean up global variable shadowing in acpi_pcihp_init()Philippe Mathieu-Daudé1-3/+2
Fix: hw/acpi/pcihp.c:499:36: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] MemoryRegion *address_space_io, ^ include/exec/address-spaces.h:35:21: note: previous declaration is here extern AddressSpace address_space_io; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ani Sinha <anisinha@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231010115048.11856-5-philmd@linaro.org>
2023-10-19hw/sparc64/ebus: Access memory regions via pci_address_space_io()Philippe Mathieu-Daudé1-4/+4
PCI functions are plugged on a PCI bus. They can only access external memory regions via the bus. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231011185954.10337-5-philmd@linaro.org>
2023-10-19hw/pci-host/sh_pcic: Replace magic value by proper definitionPhilippe Mathieu-Daudé1-2/+3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20231012041237.22281-4-philmd@linaro.org>
2023-10-19hw/pci-host/sh_pcic: Correct PCI host / devfn#0 function namesPhilippe Mathieu-Daudé1-8/+8
Host bridge device and PCI function #0 are inverted. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20231012041237.22281-3-philmd@linaro.org>
2023-10-19hw/pci-host/sh_pcic: Declare CPU QOM types using DEFINE_TYPES() macroPhilippe Mathieu-Daudé1-23/+17
When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20231012041237.22281-2-philmd@linaro.org>
2023-10-19hw/misc/mips_itu: Make MIPSITUState target agnosticPhilippe Mathieu-Daudé1-2/+2
When prototyping a heterogenous machine including the ITU, we get: include/hw/misc/mips_itu.h:76:5: error: unknown type name 'MIPSCPU' MIPSCPU *cpu0; ^ MIPSCPU is declared in the target specific "cpu.h" header, but we don't want to include it, because "cpu.h" is target specific and its inclusion taints all files including "mips_itu.h", which become target specific too. We can however use the 'ArchCPU *' type in the public header. By keeping the TYPE_MIPS_CPU QOM type check in the link property declaration, QOM core code will still check the property is a correct MIPS CPU. TYPE_MIPS_ITU is still built per-(MIPS)target, but its header can now be included by other targets. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231009171443.12145-4-philmd@linaro.org>
2023-10-19hw/mips: Merge 'hw/mips/cpudevs.h' with 'target/mips/cpu.h'Philippe Mathieu-Daudé7-7/+0
"hw/mips/cpudevs.h" contains declarations which are specific to the MIPS architecture; it doesn't make sense for these to be called from a non-MIPS architecture. Move the declarations to "target/mips/cpu.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231009171443.12145-2-philmd@linaro.org>
2023-10-19hw/mips/malta: Use sdram_type enum from 'hw/i2c/smbus_eeprom.h'Philippe Mathieu-Daudé1-1/+1
Since commit 93198b6cad ("i2c: Split smbus into parts") the SDRAM types are enumerated as sdram_type in "hw/i2c/smbus_eeprom.h". Using the enum removes this global shadow warning: hw/mips/malta.c:209:12: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] enum { SDR = 0x4, DDR2 = 0x8 } type; ^ include/hw/i2c/smbus_eeprom.h:33:19: note: previous declaration is here enum sdram_type { SDR = 0x4, DDR = 0x7, DDR2 = 0x8 }; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231009092127.49778-1-philmd@linaro.org>
2023-10-19hw/sd/sdhci: Block Size Register bits [14:12] is lostLu Gao1-4/+11
Block Size Register bits [14:12] is SDMA Buffer Boundary, it is missed in register write, but it is needed in SDMA transfer. e.g. it will be used in sdhci_sdma_transfer_multi_blocks to calculate boundary_ variables. Missing this field will cause wrong operation for different SDMA Buffer Boundary settings. Fixes: d7dfca0807 ("hw/sdhci: introduce standard SD host controller") Fixes: dfba99f17f ("hw/sdhci: Fix DMA Transfer Block Size field") Signed-off-by: Lu Gao <lu.gao@verisilicon.com> Signed-off-by: Jianxian Wen <jianxian.wen@verisilicon.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-ID: <20220321055618.4026-1-lu.gao@verisilicon.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-10-19memory: follow Error API guidelinesMarc-André Lureau1-3/+3
Return true/false on success/failure. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231009075310.153617-1-marcandre.lureau@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-10-19hw/timer/npcm7xx_timer: Prevent timer from counting down past zeroChris Rauer1-0/+3
The counter register is only 24-bits and counts down. If the timer is running but the qtimer to reset it hasn't fired off yet, there is a chance the regster read can return an invalid result. Signed-off-by: Chris Rauer <crauer@google.com> Message-id: 20230922181411.2697135-1-crauer@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-19target/arm/arm-powerctl: Correctly init CPUs when powered on to lower ELPeter Maydell1-72/+23
The code for powering on a CPU in arm-powerctl.c has two separate use cases: * emulation of a real hardware power controller * emulation of firmware interfaces (primarily PSCI) with CPU on/off APIs For the first case, we only need to reset the CPU and set its starting PC and X0. For the second case, because we're emulating the firmware we need to ensure that it's in the state that the firmware provides. In particular, when we reset to a lower EL than the highest one we are emulating, we need to put the CPU into a state that permits correct running at that lower EL. We already do a little of this in arm-powerctl.c (for instance we set SCR_HCE to enable the HVC insn) but we don't do enough of it. This means that in the case where we are emulating EL3 but also providing emulated PSCI the guest will crash when a secondary core tries to use a feature that needs an SCR_EL3 bit to be set, such as MTE or PAuth. The hw/arm/boot.c code also has to support this "start guest code in an EL that's lower than the highest emulated EL" case in order to do direct guest kernel booting; it has all the necessary initialization code to set the SCR_EL3 bits. Pull the relevant boot.c code out into a separate function so we can share it between there and arm-powerctl.c. This refactoring has a few code changes that look like they might be behaviour changes but aren't: * if info->secure_boot is false and info->secure_board_setup is true, then the old code would start the first CPU in Hyp mode but without changing SCR.NS and NSACR.{CP11,CP10}. This was wrong behaviour because there's no such thing as Secure Hyp mode. The new code will leave the CPU in SVC. (There is no board which sets secure_boot to false and secure_board_setup to true, so this isn't a behaviour change for any of our boards.) * we don't explicitly clear SCR.NS when arm-powerctl.c does a CPU-on to EL3. This was a no-op because CPU reset will reset to NS == 0. And some real behaviour changes: * we no longer set HCR_EL2.RW when booting into EL2: the guest can and should do that themselves before dropping into their EL1 code. (arm-powerctl and boot did this differently; I opted to use the logic from arm-powerctl, which only sets HCR_EL2.RW when it's directly starting the guest in EL1, because it's more correct, and I don't expect guests to be accidentally depending on our having set the RW bit for them.) * if we are booting a CPU into AArch32 Secure SVC then we won't set SCR.HCE any more. This affects only the vexpress-a15 and raspi2b machine types. Guests booting in this case will either: - be able to set SCR.HCE themselves as part of moving from Secure SVC into NS Hyp mode - will move from Secure SVC to NS SVC, and won't care about behaviour of the HVC insn - will stay in Secure SVC, and won't care about HVC * on an arm-powerctl CPU-on we will now set the SCR bits for pauth/mte/sve/sme/hcx/fgt features The first two of these are very minor and I don't expect guest code to trip over them, so I didn't judge it worth convoluting the code in an attempt to keep exactly the same boot.c behaviour. The third change fixes issue 1899. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1899 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230926155619.4028618-1-peter.maydell@linaro.org
2023-10-19hw/arm/smmuv3: Advertise SMMUv3.1-XNX featurePeter Maydell1-0/+4
The SMMUv3.1-XNX feature is mandatory for an SMMUv3.1 if S2P is supported, so we should theoretically have implemented it as part of the recent S2P work. Fortunately, for us the implementation is a no-op. This feature is about interpretation of the stage 2 page table descriptor XN bits, which control execute permissions. For QEMU, the permission bits passed to an IOMMU (via MemTxAttrs and IOMMUAccessFlags) only indicate read and write; we do not distinguish data reads from instruction reads outside the CPU proper. In the SMMU architecture's terms, our interconnect between the client device and the SMMU doesn't have the ability to convey the INST attribute, and we therefore use the default value of "data" for this attribute. We also do not support the bits in the Stream Table Entry that can override the on-the-bus transaction attribute permissions (we do not set SMMU_IDR1.ATTR_PERMS_OVR=1). These two things together mean that for our implementation, it never has to deal with transactions with the INST attribute, and so it can correctly ignore the XN bits entirely. So we already implement FEAT_XNX's "XN field is now 2 bits, not 1" behaviour to the extent that we need to. Advertise the presence of the feature in SMMU_IDR3.XNX. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20230914145705.1648377-4-peter.maydell@linaro.org
2023-10-19hw/arm/smmuv3: Sort ID register setting into field orderPeter Maydell1-2/+2
In smmuv3_init_regs() when we set the various bits in the ID registers, we do this almost in order of the fields in the registers, but not quite. Move the initialization of SMMU_IDR3.RIL and SMMU_IDR5.OAS into their correct places. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20230914145705.1648377-3-peter.maydell@linaro.org
2023-10-19hw/arm/smmuv3: Update ID register bit field definitionsPeter Maydell1-0/+38
Update the SMMUv3 ID register bit field definitions to the set in the most recent specification (IHI0700 F.a). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20230914145705.1648377-2-peter.maydell@linaro.org
2023-10-19hw/arm/sbsa-ref: use bsa.h for PPI definitionsLeif Lindholm1-12/+9
Use the private peripheral interrupt definitions from bsa.h instead of defining them locally. Refactor to use the INTIDs defined there instead of the PPI# used previously. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20230919090229.188092-4-quic_llindhol@quicinc.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-19{include/}hw/arm: refactor virt PPI logicLeif Lindholm2-16/+20
GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31. As in, PPI0 is INTID16 .. PPI15 is INTID31. Arm's Base System Architecture specification (BSA) lists the mandated and recommended private interrupt IDs by INTID, not by PPI index. But current definitions in virt define them by PPI index, complicating cross referencing. Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value, converting a PPI index to an INTID. Resolve this by redefining the BSA-allocated PPIs by their INTIDs, and replacing the PPI(x) macro with an INTID_TO_PPI(x) one where required. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20230919090229.188092-2-quic_llindhol@quicinc.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-19xlnx-versal-efuse: hw/nvram: Remove deprecated device resetTong Ho1-3/+5
This change implements the ResettableClass interface for the device. Signed-off-by: Tong Ho <tong.ho@amd.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-id: 20231004055339.323833-1-tong.ho@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-19xlnx-zynqmp-efuse: hw/nvram: Remove deprecated device resetTong Ho1-3/+5
This change implements the ResettableClass interface for the device. Signed-off-by: Tong Ho <tong.ho@amd.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-id: 20231004055713.324009-1-tong.ho@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-19xlnx-bbram: hw/nvram: Remove deprecated device resetTong Ho1-3/+5
This change implements the ResettableClass interface for the device. Signed-off-by: Tong Ho <tong.ho@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231003052345.199725-1-tong.ho@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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