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2014-06-16spapr_iommu: Introduce bus_offset in sPAPRTCETableAlexey Kardashevskiy3-6/+13
This adds @bus_offset into sPAPRTCETable to tell where TCE table starts from. It is set to 0 for emulated devices. Dynamic DMA windows will use other offset. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_iommu: Introduce page_shift in sPAPRTCETableAlexey Kardashevskiy3-26/+47
At the moment only 4K pages are supported by sPAPRTCETable. Since sPAPR spec allows other page sizes and we are going to implement them, we need page size to be configrable. This adds @page_shift into sPAPRTCETable and replaces SPAPR_TCE_PAGE_SHIFT with it where it is possible. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_iommu: Get rid of window_size in sPAPRTCETableAlexey Kardashevskiy3-33/+22
This removes window_size as it is basically a copy of nb_table shifted by SPAPR_TCE_PAGE_SHIFT. As new dynamic DMA windows are going to support windows as big as the entire RAM and this number will be bigger that 32 capacity, we will have to do something about @window_size anyway and removal seems to be the right way to go. This removes dma_window_start/dma_window_size from sPAPRPHBState as they are no longer used. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_iommu: Convert old qdev_init_nofail() to object_property_set_boolAlexey Kardashevskiy1-1/+1
qdev_init_nofail() was replaced by object_property_set_bool("realized") all over the QEMU so do we. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_pci: Allow multiple TCE tables per PHBAlexey Kardashevskiy1-11/+43
At the moment sPAPRPHBState contains a @tcet pointer to the only TCE table. However sPAPR spec allows having more than one DMA window. Since the TCE object is already a child of SPAPR PHB object, there is no need to keep an additional pointer to it in sPAPRPHBState so remove it. This changes the way sPAPRPHBState::reset performs reset of sPAPRTCETable objects. This changes the default DMA window properties calculation. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_pci: spapr_iommu: Make DMA window a subregionAlexey Kardashevskiy2-3/+19
Currently the default DMA window is represented by a single MemoryRegion. However there can be more than just one window so we need a "root" memory region to be separated from the actual DMA window(s). This introduces a "root" IOMMU memory region and adds a subregion for the default DMA 32bit window. Following patches will add other subregion(s). This initializes a default DMA window subregion size to the guest RAM size as this window can be switched into "bypass" mode which implements direct DMA mapping. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_pci: Introduce a finish_realize() callbackAlexey Kardashevskiy1-12/+26
The spapr-pci PHB initializes IOMMU for emulated devices only. The upcoming VFIO support will do it different. However both emulated and VFIO PHB types share most of the initialization code. For the type specific things a new finish_realize() callback is introduced. This introduces sPAPRPHBClass derived from PCIHostBridgeClass and adds the callback pointer. This implements finish_realize() for emulated devices. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: Fix compilation] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_iommu: Enable multiple TCE requestsAlexey Kardashevskiy2-0/+81
Currently only single TCE entry per request is supported (H_PUT_TCE). However PAPR+ specification allows multiple entry requests such as H_PUT_TCE_INDIRECT and H_STUFF_TCE. Having less transitions to the host kernel via ioctls, support of these calls can accelerate IOMMU operations. This implements H_STUFF_TCE and H_PUT_TCE_INDIRECT. This advertises "multi-tce" capability to the guest if the host kernel supports it (KVM_CAP_SPAPR_MULTITCE) or guest is running in TCG mode. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Enable dynamic change of the supported hypercalls listAlexey Kardashevskiy1-7/+23
At the moment the "ibm,hypertas-functions" list is fixed. However some calls should be listed there if they are supported by QEMU or the host kernel. This enables hyperrtas_prop to grow on stack by adding a SPAPR_HYPERRTAS_ADD macro. "qemu,hypertas-functions" is converted as well. The first user of this is going to be a "multi-tce" property. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16macio: Fix timer endiannessAlexander Graf1-1/+1
The timer registers on our KeyLargo macio emulation are read as byte reversed from the big endian guest, so we better expose them endian reversed as well. This fixes initial hickups of booting Mac OS X with -M mac99 for me. Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-06-16macio ide: Do remainder access asynchronouslyAlexander Graf2-10/+46
The macio IDE controller has some pretty nasty magic in its implementation to allow for unaligned sector accesses. We used to handle these accesses synchronously inside the IO callback handler. However, the block infrastructure changed below our feet and now it's impossible to call a synchronous block read/write from the aio callback handler of a previous block access. Work around that limitation by making the unaligned handling bits also go through our asynchronous handler. This fixes booting Mac OS X for me. Reported-by: John Arbuckle <programmingkidx@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_iommu: Replace @instance_id with LIOBN for migrationAlexey Kardashevskiy1-1/+3
SPAPR IOMMU is a bus-less device and therefore its only ID in migration stream is an instance id which is not reliable ID as it depends on the command line parameters order. Since libvirt may change the order, we need something better than that. This removes VMSD descriptor from the class definitiion and registers it with @liobn as an intance ID to let the destination side find the right device to receive migration data. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Implement processor compatibility in ibm, client-architecture-supportAlexey Kardashevskiy2-1/+109
Modern Linux kernels support last POWERPC CPUs so when a kernel boots, in most cases it can find a matching cpu_spec in the kernel's cpu_specs list. However if the kernel is quite old, it may be missing a definition of the actual CPU. To provide an ability for old kernels to work on modern hardware, a Processor Compatibility Mode has been introduced by the PowerISA specification. >From the hardware prospective, it is supported by the Processor Compatibility Register (PCR) which is defined in PowerISA. The register enables one of the compatibility modes (2.05/2.06/2.07). Since PCR is a hypervisor privileged register and cannot be directly accessed from the guest, the mode selection is done via ibm,client-architecture-support (CAS) RTAS call using which the guest specifies what "raw" and "architected" CPU versions it supports. QEMU works out the best match, changes a "cpu-version" property of every CPU and notifies the guest about the change by setting these properties in the buffer passed as a response on a custom H_CAS hypercall. This implements ibm,client-architecture-support parameters parsing (now only for PVRs) and cooks the device tree diff with new values for "cpu-version", "ibm,ppc-interrupt-server#s" and "ibm,ppc-interrupt-server#s" properties. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Limit threads per core according to current compatibility modeAlexey Kardashevskiy1-1/+1
This puts a limit to the number of threads per core based on the current compatibility mode. Although PowerISA specs do not specify the maximum threads per core number, the linux guest still expects that PowerISA2.05-compatible CPU supports only 2 threads per core as this is what POWER6 (2.05 compliant CPU) implements, the same is for POWER7 (2.06, 4 threads) and POWER8 (2.07, 8 threads). This calls spapr_fixup_cpu_smt_dt() with the maximum allowed number of threads which affects ibm,ppc-interrupt-server#s and ibm,ppc-interrupt-gserver#s properties. The number of CPU nodesremains unchanged. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Rework spapr_fixup_cpu_dt()Alexey Kardashevskiy1-11/+22
In PPC code we usually use the "cs" name for a CPUState* variables and "cpu" for PowerPCCPU. So let's change spapr_fixup_cpu_dt() to use same rules as spapr_create_fdt_skel() does. This adds missing nodes creation if they do not already exist in the current device tree, this is going to be used from the client-architecture-support handler. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Add ibm, client-architecture-support callAlexey Kardashevskiy2-0/+57
The PAPR+ specification defines a ibm,client-architecture-support (CAS) RTAS call which purpose is to provide a negotiation mechanism for the guest and the hypervisor to work out the best compatibility parameters. During the negotiation process, the guest provides an array of various options and capabilities which it supports, the hypervisor adjusts the device tree and (optionally) reboots the guest. At the moment the Linux guest calls CAS method at early boot so SLOF gets called. SLOF allocates a memory buffer for the device tree changes and calls a custom KVMPPC_H_CAS hypercall. QEMU parses the options, composes a diff for the device tree, copies it to the buffer provided by SLOF and returns to SLOF. SLOF updates the device tree and returns control to the guest kernel. Only then the Linux guest parses the device tree so it is possible to avoid unnecessary reboot in most cases. The device tree diff is a header with an update format version (defined as 1 in this patch) followed by a device tree with the properties which require update. If QEMU detects that it has to reboot the guest, it silently does so as the guest expects reboot to happen because this is usual pHyp firmware behavior. This defines custom KVMPPC_H_CAS hypercall. The current SLOF already has support for it. This implements stub which returns very basic tree (root node, no properties) to the guest. As the return buffer does not contain any change, no change in behavior is expected. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Implement "compat" CPU optionAlexey Kardashevskiy1-0/+14
This adds basic support for the "compat" CPU option. By specifying the compat property, the user can manually switch guest CPU mode from "raw" to "architected". This defines feature disable bits which are not used yet as, for example, PowerISA 2.07 says if 2.06 mode is selected, the TM bit does not matter - transactional memory (TM) will be disabled because 2.06 does not define it at all. The same is true for VSX and 2.05 mode. So just setting a mode must be ok. This does not change the existing behavior as the actual compatibility mode support is coming in next patches. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: fix compilation on 32bit hosts] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Move SMT-related properties out of skeleton fdtAlexey Kardashevskiy1-15/+33
The upcoming support of the "ibm,client-architecture-support" reconfiguration call will be able to change dynamically the number of threads per core (SMT mode). From the device tree prospective this does not change the number of CPU nodes (as it is one node per a CPU core) but affects content and size of the ibm,ppc-interrupt-server#s and ibm,ppc-interrupt-gserver#s properties. This moves ibm,ppc-interrupt-server#s and ibm,ppc-interrupt-gserver#s out of the device tree skeleton. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: openpic_kvm: Implement resetAlexander Graf1-5/+10
When we trigger a system reset, the in-kernel openpic controller should also get reset. This happens through a write to the GCR.RESET register which is the same mechanism a guest would use to manually reset the device. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16openpic: Reset IRQ source private membersPaul Janzen1-2/+2
The openpic emulation code maintains an allowable-CPU's bitmap ("destmask") for each IRQ source which is calculated from the IDR register value whenever the guest OS writes to it. However, if the guest OS relies on the system to set the IDR register to a default value at reset, and does not write IDR, then destmask does not get updated, and interrupts do not get propagated to the guest. Additionally, if an IRQ source is marked as critical, the source's internal "output" and "nomask" fields are not correctly reset when the PIC is reset. Fix both these issues by calling write_IRQreg_idr from within openpic_reset, instead of simply setting the IDR register to the specified idr_reset value. Signed-off-by: Paul Janzen <pcj@pauljanzen.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16openpic: Move definition of openpic_resetPaul Janzen1-49/+50
This patch moves the definition of openpic_reset after the various register read/write functions. No functional change. It is in preparation for using the register read/write functions in openpic_reset. Signed-off-by: Paul Janzen <pcj@pauljanzen.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16macio: handle non-block ATAPI DMA transfersMark Cave-Ayland1-0/+21
Currently the macio DMA routines assume that all DMA requests are for read/write block transfers. This is not always the case for ATAPI, for example when requesting a TOC where the response is generated directly in the IDE buffer. Detect these non-block ATAPI DMA transfers (where no lba is specified in the command) and copy the results directly into RAM as indicated by the DBDMA descriptor. This fixes CDROM access under MorphOS. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Add ibm, chip-id property in device treeAlexey Kardashevskiy1-0/+6
This adds a "ibm,chip-id" property for CPU nodes which should be the same for all cores in the same CPU socket. The recent guest kernels use this information to associate threads with sockets. Refer to the kernel commit 256f2d4b463d3030ebc8d2b54f427543814a2bdc for more details. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Add support for time base offset migrationAlexey Kardashevskiy2-2/+81
This allows guests to have a different timebase origin from the host. This is needed for migration, where a guest can migrate from one host to another and the two hosts might have a different timebase origin. However, the timebase seen by the guest must not go backwards, and should go forwards only by a small amount corresponding to the time taken for the migration. This is only supported for recent POWER hardware which has the TBU40 (timebase upper 40 bits) register. That includes POWER6, 7, 8 but not 970. This adds kvm_access_one_reg() to access a special register which is not in env->spr. This requires kvm_set_one_reg/kvm_get_one_reg patch. The feature must be present in the host kernel. This bumps vmstate_spapr::version_id and enables new vmstate_ppc_timebase only for it. Since the vmstate_spapr::minimum_version_id remains unchanged, migration from older QEMU is supported but without vmstate_ppc_timebase. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: e500: Move to u-boot as firmwareAlexander Graf1-41/+73
Almost all platforms QEMU emulates have some sort of firmware they can load to expose a guest environment that closely resembles the way it would look like on real hardware. This patch introduces such a firmware on our e500 platforms. U-boot is the default firmware for most of these systems and as such our preferred choice. For backwards compatibility reasons (and speed and simplicity) we skip u-boot when you use -kernel and don't pass in -bios. For all other combinations like -kernel and -bios or no -kernel you get u-boot as firmware. This allows you to modify the boot environment, execute a networked boot through the e1000 emulation and execute u-boot payloads. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: e500: Expose kernel load address in dtAlexander Graf1-5/+23
We want to move to a model where firmware loads our kernel. To achieve this we need to be able to tell firmware where the kernel lies. Let's copy the mechanism we already use for -M pseries and expose the kernel load address and size through the device tree. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: e500: implement PCI INTx routingBharat Bhushan2-2/+24
This patch adds pci pin to irq_num routing callback. This callback is called from pci_device_route_intx_to_irq to find which pci device maps to which irq. This fix is required for pci-device passthrough using vfio. Also without this patch we gets below prints " PCI: Bug - unimplemented PCI INTx routing (e500-pcihost) qemu-system-ppc64: PCI: Bug - unimplemented PCI INTx routing (e500-pcihost) " and Legacy interrupt does not work with pci device passthrough. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> [agraf: remove double semicolon] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: e500: some pci related cleanupBharat Bhushan2-12/+14
- Use PCI_NUM_PINS rather than hardcoding - use "pin" wherever possible Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_pci: fix MSI limitAlexey Kardashevskiy1-16/+18
At the moment XICS does not support interrupts reuse so sPAPR PHB implements this. sPAPRPHBState holds array of 32 spapr_pci_msi to describe PCI config address, first MSI and number of MSIs. Once allocated for a device, QEMU tries reusing this config until the number of MSIs changes. Existing SPAPR guests call ibm,change-msi in a loop until the handler returns the requested number of vectors. Recently introduced check for the maximum number of MSI/MSIX vectors supported by a device only works for a device which is new for PHB's MSI cache. If it is already there, the check is not performed which leads to new IRQ block allocation. This happens during PCI hotplug even when the user hot plug the same device which he just hot unplugged. This moves the check earlier. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16mac99: Added FW_CFG_PPC_BUSFREQ to match CLOCKFREQ and TBFREQ already thereBALATON Zoltan2-2/+8
While there, also moved the hard coded value for CLOCKFREQ to a #define. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_pci: Fix number of returned vectors in ibm, change-msiAlexey Kardashevskiy1-0/+15
Current guest kernels try allocating as many vectors as the quota is. For example, in the case of virtio-net (which has just 3 vectors) the guest requests 4 vectors (that is the quota in the test) and the existing ibm,change-msi handler returns 4. But before it returns, it calls msix_set_message() in a loop and corrupts memory behind the end of msix_table. This limits the number of vectors returned by ibm,change-msi to the maximum supported by the actual device. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Cc: qemu-stable@nongnu.org [agraf: squash in bugfix from aik] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr-pci: remove io ports workaroundGreg Kurz1-11/+2
In the past, IO space could not be mapped into the memory address space so we introduced a workaround for that. Nowadays it does not look necessary so we can remove the workaround and make sPAPR PCI configuration simplier. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Acked-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_nvram: Correct max nvram sizeAlexey Kardashevskiy1-1/+1
Currently it is UINT16_MAX*16 = 65536*16 = 1048560 which is not a round number and therefore a bit confusing. This defines MAX_NVRAM_SIZE precisely as 1MB. Suggested-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16Fix typo in eTSEC Ethernet controllerFabien Chouteau1-1/+1
IRQ are lowered when ievent bit is cleared, so irq_pulse makes no sense here... Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16savevm: Remove all the unneeded version_minimum_id_old (x86)Juan Quintela64-181/+94
After previous Peter patch, they are redundant. This way we don't assign them except when needed. Once there, there were lots of case where the ".fields" indentation was wrong: .fields = (VMStateField []) { and .fields = (VMStateField []) { Change all the combinations to: .fields = (VMStateField[]){ The biggest problem (appart from aesthetics) was that checkpatch complained when we copy&pasted the code from one place to another. Signed-off-by: Juan Quintela <quintela@redhat.com> Acked-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
2014-06-16savevm: Remove all the unneeded version_minimum_id_old (ppc)Juan Quintela13-48/+24
After previous Peter patch, they are redundant. This way we don't assign them except when needed. Once there, there were lots of case where the ".fields" indentation was wrong: .fields = (VMStateField []) { and .fields = (VMStateField []) { Change all the combinations to: .fields = (VMStateField[]){ The biggest problem (appart from aesthetics) was that checkpatch complained when we copy&pasted the code from one place to another. Signed-off-by: Juan Quintela <quintela@redhat.com> Acked-by: Alexey Kardashevskiy <aik@ozlabs.ru>
2014-06-13Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20140613-1' into ↵Peter Maydell1-0/+13
staging usb-host: add range checks for usb-host parameters # gpg: Signature made Fri 13 Jun 2014 12:33:05 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-usb-20140613-1: usb-host: add range checks for usb-host parameters Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-13Merge remote-tracking branch 'remotes/spice/tags/pull-spice-20140613-1' into ↵Peter Maydell2-1/+11
staging spice: add mouse cursor support qxl-render: add sanity check # gpg: Signature made Fri 13 Jun 2014 12:22:45 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/spice/tags/pull-spice-20140613-1: qxl-render: add sanity check spice: add mouse cursor support Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-13usb-host: add range checks for usb-host parametersGerd Hoffmann1-0/+13
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-06-13qxl-render: add sanity checkGerd Hoffmann1-0/+6
Verify dirty rectangle is completely within the primary surface, just ignore it in case it isn't. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-06-13spice: add mouse cursor supportGerd Hoffmann1-1/+5
So you'll have a mouse pointer when running non-qxl gfx cards with mouse pointer support (virtio-gpu, IIRC vmware too). Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-06-13audio: Drop superfluous conditionals around g_free()Markus Armbruster1-3/+1
Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-06-11vhost: replace ffsl with ctzlNatanael Copa1-4/+2
Avoid using the GNU extesion ffsl which is not implemented in musl libc. The atomic_xchg() means we know that vhost_log_chunk_t will never be larger than the 'long' type, so ctzl() is always sufficient. See also commit fbeadf50 (bitops: unify bitops_ffsl with the one in host-utils.h, call it bitops_ctzl) on why ctzl should be used instead of ffsl. Signed-off-by: Natanael Copa <ncopa@alpinelinux.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-10virtio.c: fix error messageMichael Tokarev1-1/+1
Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10hw: vmware_vga: don't return cursorx when the driver asks for cursory registerNicolas Owens1-1/+1
hello qemu-*@nongnu.org, this is my first contribution. apologies if something is incorrect. this patch fixes vmware_vga.c so that it actually returns the cursory register when asked for, instead of cursorx. Signed-off-by: Nicolas Owens <mischief@offblast.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10smbios: use g_free directly on NULL pointersPaolo Bonzini1-7/+2
No need to wrap it with an if. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Benoit Canet <benoit@irqsave.net> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10apb: Fix compiler warnings (large constants)Stefan Weil1-2/+2
Both constants need more than 32 bit. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10hw/net/ne2000-isa: Register vmstate structPeter Maydell1-0/+1
The ne2000-isa device defines a VMState struct for migration, but we forgot to actually register it. Correct this deficiency by setting dc->vmsd. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10hw/misc/milkymist-softusb: Remove unused softusb_{read, write}_pmem()Peter Maydell1-25/+0
The functions softusb_read_pmem() and softusb_write_pmem() are unused; remove them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10hw/isa/pc87312: Remove unused function is_parallel_epp()Peter Maydell1-5/+0
The function is_parallel_epp() is unused; remove it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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