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2015-12-22ipmi: Add an external connection simulation interfaceCorey Minyard2-0/+479
This adds an interface for IPMI that connects to a remote BMC over a chardev (generally a TCP socket). The OpenIPMI lanserv simulator describes this interface, see that for interface details. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-12-22ipmi: Add a local BMC simulationCorey Minyard2-0/+1727
This provides a minimal local BMC, basically enough to comply with the spec and provide a complete watchdog timer (including a sensor, SDR, and event). Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-12-22Add a base IPMI interfaceCorey Minyard3-0/+127
Add the basic IPMI types and infrastructure to QEMU. Low-level interfaces and simulation interfaces will register with this; it's kind of the go-between to tie them together. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-12-22q35: Remove MCHPCIState.guest_info fieldEduardo Habkost1-1/+0
The field is not used for anything. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2015-12-22hw/i386: extend pxb query for all PC machinesMarcel Apfelbaum4-3/+4
Add bus property to PC machines and use it when looking for primary PCI root bus (bus 0). Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com>
2015-12-22hw/pxb: introduce pxb-pcie expander for PCIe machinesMarcel Apfelbaum1-15/+83
The pxb-pcie is the counterpart of pxb for PCI express machines. The new device re-uses the pxb code, but appears to the guests as a different device. The pxb-pcie device does not have an internal pci-pci bridge and exposes a PCIe root bus instead of a PCI one. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-12-22hw/acpi: merge pxb adjacent memory/IO rangesMarcel Apfelbaum1-49/+74
A generic PCI Bus Expander doesn't necessary have a built-in PCI bridge. Int this case the ACPI will include IO/MEM ranges per device. Try to merge adjacent resources to reduce the ACPI tables length. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-12-22pc: Move option_rom_has_mr/rom_file_has_mr globals to MachineClassEduardo Habkost4-11/+12
This way, these settings can be simply set on the corresponding machine_options() function, instead of requiring code in pc_compat_*() functions. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2015-12-22pc: Remove enforce-aligned-dimm QOM propertyEduardo Habkost1-11/+0
The property is read-only and not used for anything. Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-12-22pc: Move enforce_aligned_dimm to PCMachineClassEduardo Habkost3-11/+9
enforce_aligned_dimm never changes after the machine is initialized, so it can be simply set in PCMachineClass like all the other compat fields. Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-12-22pc: Move acpi_data_size global to PCMachineClassEduardo Habkost3-13/+8
This way we don't need code in pc_compat_*() functions to set the legacy acpi_data_size value. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2015-12-22pc: Move legacy_acpi_table_size global to PCMachineClassEduardo Habkost1-21/+19
This way we can set legacy_acpi_table_size on the machine_options() functions, instead of requirng code in pc_compat_*() functions. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2015-12-22pc: Move compat boolean globals to PCMachineClassEduardo Habkost3-74/+72
This way the compat flags can be initialized in the machine_options() function. This will help us to eventually eliminate the pc_compat_*() functions. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2015-12-22sdhci: add optional quirk property to disable card insertion/removal interruptsAndrew Baumann1-1/+4
This is needed for a quirk of the Raspberry Pi (bcm2835/6) MMC controller, where the card insert bit is documented as unimplemented (always reads zero, doesn't generate interrupts) but is in fact observed on hardware as set at power on, but is cleared (and remains clear) on subsequent controller resets. Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1450738069-18664-4-git-send-email-Andrew.Baumann@microsoft.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-12-22sdhci: don't raise a command index error for an unexpected responseAndrew Baumann1-3/+0
This deletes a block of code that raised a command index error if a command returned response data, but the guest did not set the appropriate bits in the response register to handle such a response. I cannot find any documentation that suggests the controller should behave in this way, the error code doesn't make sense (command index error is defined for the case where the index in a response does not match that of the issued command), and in at least one case (CMD23 issued by UEFI on Raspberry Pi 2), actual hardware does not do this. Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1450738069-18664-3-git-send-email-Andrew.Baumann@microsoft.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-12-22sd: sdhci: Delete over-zealous power checkPeter Crosthwaite1-1/+1
This check was conditionalising SD card operation on the card being powered by the SDHCI host controller. It is however possible (particularly in embedded systems) for the power control of the SD card to be managed outside of SDHCI. This can be as trivial as hard-wiring the SD slot VCC to a constant power-rail. This means the guest SDHCI can validly opt-out of the SDHCI power control feature while still using the card. So delete this check to allow operation of the card with SDHCI power control. This is needed for at least Xilinx Zynq and Raspberry Pi, and also makes Freescale i.MX25 work for me. The digilent Zybo board has a public schematic which shows SD VCC hardwiring: http://digilentinc.com/Data/Products/ZYBO/ZYBO_sch_VB.3.pdf bottom of page 3. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1450738069-18664-2-git-send-email-Andrew.Baumann@microsoft.com [AB: Add Pi to list of devices fixed in commit message] Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-12-22block: replace IOV_MAX with BlockLimits.max_iovStefan Hajnoczi1-1/+1
Request merging must not result in a huge request that exceeds the maximum number of iovec elements. Use BlockLimits.max_iov instead of hardcoding IOV_MAX. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-12-22virtio-blk: trivial code optimizationGonglei1-18/+10
1. avoid possible superflous checking 2. make code more robustness ["make code more robustness" refers to avoiding integer underflows/overflows. --Stefan] Signed-off-by: Gonglei <arei.gonglei@huawei.com> Message-id: 1447207166-12612-1-git-send-email-arei.gonglei@huawei.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-12-18xenfb: avoid reading twice the same fields from the shared pageStefano Stabellini1-4/+6
Reading twice the same field could give the guest an attack of opportunity. In the case of event->type, gcc could compile the switch statement into a jump table, effectively ending up reading the type field multiple times. This is part of XSA-155. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2015-12-18xen/blkif: Avoid double access to src->nr_segmentsStefano Stabellini1-4/+8
src is stored in shared memory and src->nr_segments is dereferenced twice at the end of the function. If a compiler decides to compile this into two separate memory accesses then the size limitation could be bypassed. Fix it by removing the double access to src->nr_segments. This is part of XSA-155. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2015-12-17scsi: always call notifier on async cancellationPaolo Bonzini1-3/+0
This was found by code inspection. If the request is cancelled twice, the notifier is never called on the second cancellation request, and hence for example a TMF might never finish. All the calls in scsi_req_cancel_async are idempotent, so the change is safe. Reviewed-by: Fam Zheng <famz@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1450290827-30508-2-git-send-email-pbonzini@redhat.com>
2015-12-17scsi: use scsi_req_cancel_async when purging requestsPaolo Bonzini1-2/+4
This avoids calls to aio_poll without having acquired the context first. Reviewed-by: Fam Zheng <famz@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1450290827-30508-1-git-send-email-pbonzini@redhat.com>
2015-12-17cris: avoid "naked" qemu_logPaolo Bonzini1-1/+1
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17alpha: convert "naked" qemu_log to tracepointPaolo Bonzini1-1/+2
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17kvm: x86: add support for KVM_CAP_SPLIT_IRQCHIPPaolo Bonzini3-6/+71
This patch adds support for split IRQ chip mode. When KVM_CAP_SPLIT_IRQCHIP is enabled: 1.) The PIC, PIT, and IOAPIC are implemented in userspace while the LAPIC is implemented by KVM. 2.) The software IOAPIC delivers interrupts to the KVM LAPIC via kvm_set_irq. Interrupt delivery is configured via the MSI routing table, for which routes are reserved in target-i386/kvm.c then configured in hw/intc/ioapic.c 3.) KVM delivers IOAPIC EOIs via a new exit KVM_EXIT_IOAPIC_EOI, which is handled in target-i386/kvm.c and relayed to the software IOAPIC via ioapic_eoi_broadcast. Signed-off-by: Matt Gingell <gingell@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17kvm: add support for -machine kernel_irqchip=splitMatt Gingell2-8/+42
This patch adds the initial plumbing for split IRQ chip mode via KVM_CAP_SPLIT_IRQCHIP. In addition to option processing, a number of kvm_*_in_kernel macros are defined to help clarify which component is where. Signed-off-by: Matt Gingell <gingell@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17hw/misc: Hyper-V test device 'hyperv-testdev'Andrey Smetanin2-0/+168
'hyperv-testdev' will be used by kvm-unit-tests to setup Hyper-V SynIC SINT's routing and to inject Hyper-V SynIC SINT's. Hyper-V test device is ISA type device that creates 0x3000 IO memory region and catches write access into it. Every write operation data decoded into ctl code and parameters for Hyper-V test device. Signed-off-by: Andrey Smetanin <asmetanin@virtuozzo.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> CC: "Andreas Färber" <afaerber@suse.de> CC: Marcelo Tosatti <mtosatti@redhat.com> CC: Roman Kagan <rkagan@virtuozzo.com> CC: Denis V. Lunev <den@openvz.org> CC: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17linux-headers: update from kvm/nextPaolo Bonzini1-2/+2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17vmw_pvscsi: Introduce 'x-disable-pcie' backword compatability propertyShmulik Ladkani1-0/+2
Following the previous patch which changed pvscsi to be a pci express device, this patch introduces a boolean property 'x-disable-pcie'. Its default value is false, exposing pvscsi as a pcie device. Setting 'x-disable-pcie' to 'on' preserves the old 'pci device' (non express) behavior. This allows migration to older versions. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Message-Id: <1449994112-7054-7-git-send-email-shmulik.ladkani@ravellosystems.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17vmw_pvscsi: The pvscsi device is a PCIE endpointShmulik Ladkani1-1/+53
Report the 'express endpoint' capability if on a PCIE bus. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Message-Id: <1449994112-7054-6-git-send-email-shmulik.ladkani@ravellosystems.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17vmw_pvscsi: coding: Introduce PVSCSIClassShmulik Ladkani1-0/+10
Introduce a class type for pvscsi, and the usual DEVICE_CLASS/DEVICE_GET_CLASS macros. No semantic change. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Message-Id: <1449994112-7054-5-git-send-email-shmulik.ladkani@ravellosystems.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17vmw_pvscsi: Introduce 'x-old-pci-configuration' backword compatability propertyShmulik Ladkani1-0/+2
Following the previous patches, which introduced various changes in pvscsi's pci configuration space (device subsystem id and revision, msi offset), this patch introduces a boolean property 'x-old-pci-configuration' to pvscsi. Its default value is false, exposing the above changes in the pci config space. Setting 'x-old-pci-configuration' to 'on' preserves the old behavior, which allows migration to older versions. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Message-Id: <1449994112-7054-4-git-send-email-shmulik.ladkani@ravellosystems.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17vmw_pvscsi: Change offset of msi pci capabilityShmulik Ladkani1-2/+3
Place device reported MSI capability at the same offset as placed by the VMware virtual hardware - at offset 0x7c. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Message-Id: <1449994112-7054-3-git-send-email-shmulik.ladkani@ravellosystems.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17vmw_pvscsi: Set device subsystem and revisionShmulik Ladkani1-3/+20
To be VMware PVSCSI SCSI Controller, rev 02. As reported by the VMware virtual hardware. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Message-Id: <1449994112-7054-2-git-send-email-shmulik.ladkani@ravellosystems.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17i.MX: Add an i.MX25 specific CCM class/instanceJean-Christophe Dubois3-1/+343
With this CCM, i.MX25 timer is accurate with "real world time". Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 2c0cf90be767bfc8520661eca891ab22c61f18fe.1449528242.git.jcd@tribudubois.net Reviewed-by Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17i.MX: Split the CCM class into an abstract base class and a concrete classJean-Christophe Dubois5-215/+421
The IMX_CCM class is now the base abstract class that is used by EPIT and GPT timer implementation. IMX31_CCM class is the concrete class implementing CCM for i.MX31 SOC. For now the i.MX25 continues to use the i.MX31 CCM implementation. An i.MX25 specific CCM will be introduced in a later patch. We also rework initialization to stop using deprecated sysbus device init. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: fd3c7f87b50f5ebc99ec91f01413db35017f116d.1449528242.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17i.MX: rename i.MX CCM get_clock() function and CLK ID enum namesJean-Christophe Dubois3-23/+21
This is to prepare for CCM code refactoring. This is just a bit of function and enum values renaming. We also remove some useless intermediate variables. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 53c4d9b9611988a5f56f178f285e04490747925e.1449528242.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17i.MX: Fix i.MX31 default/reset configurationJean-Christophe Dubois1-1/+1
Linux on i.MX31/KZM is expecting the CCM to use the CKIH ref clock instead of the CKIL plus the FPM multiplier. We change the CCMR reg reset value to match linux expected config. This allows the CCM to provide a 39MHz clk (as expected by linux) instead of the actual 50MHz. With this change the "sleep 60" command on linux is time accurate with "real world time". Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 6dc5bc4e0a450b20cecdb2991112e7281b653345.1449528242.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ARM: Virt: Add gpio-keys node for Poweroff using DTShannon Zhao1-0/+16
Add a gpio-keys node. This is used for Poweroff for the systems which use DT not ACPI. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1449804086-3464-11-git-send-email-zhaoshenglong@huawei.com [PMM: use "standard-headers/linux/input.h" rather than <linux/input.h>] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ARM: Virt: Add QEMU powerdown notifier and hook it to GPIO Pin 3Shannon Zhao1-1/+15
Currently mach-virt model doesn't support powerdown request. Guest VM doesn't react to system_powerdown from monitor console (or QMP) because there is no communication mechanism for such requests. This patch registers GPIO Pin 3 with powerdown notification. So guest VM can receive notification when such powerdown request is triggered. Signed-off-by: Wei Huang <wei@redhat.com> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Wei Huang <wei@redhat.com> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1449804086-3464-10-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ARM: ACPI: Add _E03 for Power ButtonShannon Zhao1-0/+14
Here GPIO pin 3 is used for Power Button, add _E03 in ACPI DSDT table. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1449804086-3464-9-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ACPI: Add aml_gpio_int() wrapper for GPIO Interrupt ConnectionShannon Zhao1-0/+20
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1449804086-3464-8-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ACPI: Add GPIO Connection DescriptorShannon Zhao1-0/+68
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1449804086-3464-7-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ARM: ACPI: Add power button device in ACPI DSDT tableShannon Zhao1-0/+11
Add power button device in ACPI DSDT table. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Wei Huang <wei@redhat.com> Tested-by: Wei Huang <wei@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1449804086-3464-6-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ARM: ACPI: Add GPIO controller in ACPI DSDT tableShannon Zhao1-0/+19
Add GPIO controller in ACPI DSDT table. It can be used for gpio event. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1449804086-3464-5-git-send-email-zhaoshenglong@huawei.com Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17ARM: Virt: Add a GPIO controllerShannon Zhao1-0/+30
ACPI 5.0 supports GPIO-signaled ACPI Events. This can be used for powerdown, hotplug evnets. Add a GPIO controller in machine virt, to support powerdown, maybe can be used for cpu hotplug. And here we use pl061. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Wei Huang <wei@redhat.com> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1449804086-3464-4-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17acpi: extend aml_interrupt() to support multiple irqsIgor Mammedov2-20/+25
ASL Interrupt() macro translates to Extended Interrupt Descriptor which supports variable number of IRQs. It will be used for conversion of ASL code for pc/q35 machines that use it for returning several IRQs in _PSR object. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1449804086-3464-3-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17acpi: support serialized methodXiao Guangrong3-27/+41
Add serialized method support so that explicit Mutex can be avoided Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1449804086-3464-2-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17arm: soc-dma: use hwaddr instead of target_ulong in printfPaolo Bonzini1-22/+17
This is a first baby step towards removing widespread inclusion of cpu.h and compiling more devices once (so that arm, aarch64 and in the future target-multi can share the object files). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: changed __FUNCTION__ to __func__ since we're touching these lines of code anyway] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17arm: explicitly mark device loads as little-endianPaolo Bonzini2-6/+6
Behaviour of emulated devices should not depend on the endianness of the CPU, so avoid using the endian-dependent load and store functions in the PXA2xx and OMAP display devices. These devices are little endian when they do DMA access. (Since ARM softmmu is always compiled as little endian, this means that the endian-dependent load and store functions are always little endian, so this commit makes no functionally visible change.) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: rewrote commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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