aboutsummaryrefslogtreecommitdiff
path: root/hw
AgeCommit message (Collapse)AuthorFilesLines
2023-02-07Merge tag 'pull-aspeed-20230207' of https://github.com/legoater/qemu into ↵Peter Maydell17-111/+402
staging aspeed queue: * various small cleanups and fixes * new variant of the supermicrox11-bmc machine using an ast2500-a1 SoC * at24c_eeprom extension to define eeprom contents with static arrays * ast10x0 model and test improvements * avocado update of images to use the latest # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmPiByEACgkQUaNDx8/7 # 7KF1nw/7BxVb8bxO5T00AnGDFNahDq3ItyisrbOkElDw18oN1eULrtZFH1UopjDE # 3HKwR2nb4X7MfcLirVXXxwO1GgIxUkeCsVEY6hpg3TxDPRhPW2toNpNt/WCfFKgq # ZdYdaKgkON/xHQPv6kgQzU2n9Zpuznj0CE9A3k1mAyBcCSitsvu4TW6AQBKmLgUR # 9lu61onfX9XoPxZv3abuY3c3UyzevOc6BUT67dmr8naAhHLyBU+DWAW6Kg0Dtc9j # p+bwxIDRimK50DJt9l13OLSAJyhrW1gMsPPGb+48OClpEOhHwq8oqRuMFpbHaQ0/ # 2MMtMbavXtzBScfmLzR3yw2IwohxSXKMe+7irkJiG/hc8/gtpRATaaS+zfvS0rla # QybWYtJyjmW+QUOnmBsKGwT0PWJcOd3bKtVPgPd7WGeHGVtTBOqU/svExaO+gIv8 # uX1gOelEgLmLenUjc/Wp4cHgnePTBK8vG1g3IrEtcCblhwpr0e3/aJgHGgO3cQzH # X9P2buwHyLzjsie9S1ebG9Ceg/VsGQpxNGISZdG+Z4c3+GYu5gcGQcqIAuFmwBnE # QHSNHJXITyWjo7UuqL7e1J7vROUKn0S15V9MO/yOmZgkqubu4Gt3jGcJtIGqIBlu # MFra7SiVjKBnt6PD3aKEdD9uahbqFUfmX9411ZmYUUzpfflKnCQ= # =IY/i # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Feb 2023 08:09:05 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20230207' of https://github.com/legoater/qemu: (25 commits) aspeed/sdmc: Drop unnecessary scu include tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F hw/arm/aspeed_ast10x0: Map HACE peripheral hw/arm/aspeed_ast10x0: Map the secure SRAM hw/arm/aspeed_ast10x0: Map I3C peripheral hw/arm/aspeed_ast10x0: Add various unimplemented peripherals hw/misc/aspeed_hace: Do not crash if address_space_map() failed hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP level hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize' hw/nvram/eeprom_at24c: Make reset behavior more like hardware hw/arm/aspeed: Add aspeed_eeprom.c hw/nvram/eeprom_at24c: Add init_rom field and at24c_eeprom_init_rom helper hw/arm/aspeed: Replace aspeed_eeprom_init with at24c_eeprom_init hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boards hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mr tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK boot tests/avocado/machine_aspeed.py: update buildroot tests m25p80: Add the is25wp256 SFPD table ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-07Merge tag 'pull-riscv-to-apply-20230207' of ↵Peter Maydell6-303/+355
https://github.com/alistair23/qemu into staging Third RISC-V PR for QEMU 8.0 * Update disas for xnor/orn/andn and slli.uw * Update opentitan IRQs * Fix rom code when Zicsr is disabled * Update VS timer whenever htimedelta changes * A collection of fixes for virtulisation * Set tval for triggered watchpoints * Cleanups for board and FDT creation * Add support for the T-Head vendor extensions * A fix for virtual instr exception * Fix ctzw behavior * Fix SBI getchar handler for KVM # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmPh+QQACgkQIeENKd+X # cFSdHwf9HQkO8/zTnWUFCbLVQAV3RB32i6E26uNC4+fQBpcqRWAel2PMYGi6x0H/ # fU43B5YpS7Ddfcc1ql6pJlisqsjkIsQBYjOeUfiMozLIR0dvX14jgUMxc0A8e8sZ # uv3iRXjkVz/7bEWIdflPcaXgXh74HcQCPgMDsteluZYaz4yRGP6SvI9UJHqe4tjI # HbiYmP1pcWFGDsAlKx7KbHfH/v9CE03odN3MLzwdsGYekUaFkdLlj7hmyamnqbAh # OR1y29i2od/8uJMeIu5R8rnGdWoWetCZWP0z2xv3rrZuUzMJ6VXHcdWsY9ycomJs # rYA0NB/ezmnKX+QAf+8TzW2nybG+5Q== # =XLpK # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Feb 2023 07:08:52 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20230207' of https://github.com/alistair23/qemu: (32 commits) hw/riscv: virt: Simplify virt_{get,set}_aclint() target/riscv: fix SBI getchar handler for KVM target/riscv: fix ctzw behavior target/riscv: fix for virtual instr exception target/riscv: add a MAINTAINERS entry for XThead* extension support RISC-V: Adding XTheadFmv ISA extension RISC-V: Add initial support for T-Head C906 RISC-V: Set minimum priv version for Zfh to 1.11 RISC-V: Adding T-Head FMemIdx extension RISC-V: Adding T-Head MemIdx extension RISC-V: Adding T-Head MemPair extension RISC-V: Adding T-Head multiply-accumulate instructions RISC-V: Adding XTheadCondMov ISA extension RISC-V: Adding XTheadBs ISA extension RISC-V: Adding XTheadBb ISA extension RISC-V: Adding XTheadBa ISA extension RISC-V: Adding XTheadSync ISA extension RISC-V: Adding XTheadCmo ISA extension hw/riscv: change riscv_compute_fdt_addr() semantics hw/riscv: split fdt address calculation from fdt load ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-07Merge tag 'migration-20230206-pull-request' of ↵Peter Maydell5-19/+162
https://gitlab.com/juan.quintela/qemu into staging Migration Pull request In this try - rebase to latest upstream - same than previous patch - fix compilation on non linux (userfaultfd.h) (me) - query-migrationthreads (jiang) - fix race on reading MultiFDPages_t.block (zhenzhong) - fix flush of zero copy page send reuest (zhenzhong) Please apply. Previous try: It includes: - David Hildenbrand fixes for virtio-men - David Gilbert canary to detect problems - Fix for rdma return values (Fiona) - Peter Xu uffd_open fixes - Peter Xu show right downtime for postcopy - manish.mishra msg fix fixes - my vfio changes. Please apply. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEGJn/jt6/WMzuA0uC9IfvGFhy1yMFAmPhobYACgkQ9IfvGFhy # 1yMNaA/9EHDPqrI1HL/VkJG4nNOOsQR7RbburXEberZOzvLjnqpjUD3Ls9qV6rx+ # ieHa5T4imYJFk72Wa5vx4r1/dCjtJD2W6jg5+/0nTvYAHrs1U1VRqpuTr0HiXdbJ # ZLLCnW5eDyO3eMaOX0MUkgHgL0FNkc/Lq5ViCTFsMu9O9xMuDLLdAC3cdvslKuOu # X1gKByr9jT817Y9e36amYmRaJKC6Cr/PIekNVFu12HBW79pPusLX8KWEf4RBw4HR # sPwTvMCR/BwZ0+2Lppan60G5rt/ZxDu40oU7y+RHlfWqevl4hDM84/nhjMvEgzc5 # a4Ahe2ERGLwwnC8z3l7v9+pEzSGzDoPcnRGvZcpUpk68wTDtxd5Bdq8CwmNUfL07 # VzWcYpH0yvmwjBba9jfn9fAVgnG5rVp558XcYLIII3wEToty3UDtm43wSdj2CGr6 # cu+IPAp+n/I5G9SRYBTU9ozJz45ttnEe0hxUtZ4I3MuhzHi1VEDAqTWM/X0LyS41 # TB3Y5B2KKpJYbPyZEH4nyTeetR2k7alTFzahCgKqVfOgL0nJx54petjS1K+B1P72 # g6lhP9WnQ33W+M8S7J/aGEaDJd1lFyFB2Rdjn2ZZnASH/fR9j0mFmXWvulXtjFNp # Sfim3887+Iv4Uzw4VWEe3mM5Ypi/Ba2CmuTjy/pM08Ey8X1Qs5o= # =ZQbR # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Feb 2023 00:56:22 GMT # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full] # gpg: aka "Juan Quintela <quintela@trasno.org>" [full] # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * tag 'migration-20230206-pull-request' of https://gitlab.com/juan.quintela/qemu: (30 commits) migration: save/delete migration thread info migration: Introduce interface query-migrationthreads multifd: Fix flush of zero copy page send request multifd: Fix a race on reading MultiFDPages_t.block migration: check magic value for deciding the mapping of channels io: Add support for MSG_PEEK for socket channel migration/dirtyrate: Show sample pages only in page-sampling mode migration: Perform vmsd structure check during tests migration: Add canary to VMSTATE_END_OF_LIST migration/rdma: fix return value for qio_channel_rdma_{readv,writev} migration: Show downtime during postcopy phase virtio-mem: Proper support for preallocation with migration virtio-mem: Migrate immutable properties early virtio-mem: Fail if a memory backend with "prealloc=on" is specified migration/ram: Factor out check for advised postcopy migration/vmstate: Introduce VMSTATE_WITH_TMP_TEST() and VMSTATE_BITMAP_TEST() migration/savevm: Allow immutable device state to be migrated early (i.e., before RAM) migration/savevm: Prepare vmdesc json writer in qemu_savevm_state_setup() migration/savevm: Move more savevm handling into vmstate_save() migration/ram: Optimize ram_write_tracking_start() for RamDiscardManager ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-07aspeed/sdmc: Drop unnecessary scu includeJoel Stanley1-1/+0
The model includes aspeed_scu.h but doesn't appear to require it. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230124062022.298230-1-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4FPhilippe Mathieu-Daudé1-1/+1
This SoC uses a Cortex-M4F. QEMU only implements a M4, which is good enough. Add a TODO note in case the M4F is added. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/arm/aspeed_ast10x0: Map HACE peripheralPhilippe Mathieu-Daudé1-0/+15
Since I don't have access to the datasheet, the relevant values were found in: https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi Before on Zephyr: uart:~$ hash test sha256_test tv[0]:hash_final error sha384_test tv[0]:hash_final error sha512_test tv[0]:hash_final error [00:00:06.278,000] <err> hace_global: HACE poll timeout [00:00:09.324,000] <err> hace_global: HACE poll timeout [00:00:12.261,000] <err> hace_global: HACE poll timeout uart:~$ crypto aes256_cbc_vault aes256_cbc vault key 1 [00:00:06.699,000] <inf> hace_global: aspeed_crypto_session_setup [00:00:06.699,000] <inf> hace_global: data->cmd: 1c2098 [00:00:06.699,000] <inf> hace_global: crypto_data_src: 93340 [00:00:06.699,000] <inf> hace_global: crypto_data_dst: 93348 [00:00:06.699,000] <inf> hace_global: crypto_ctx_base: 93300 [00:00:06.699,000] <inf> hace_global: crypto_data_len: 80000040 [00:00:06.699,000] <inf> hace_global: crypto_cmd_reg: 11c2098 [00:00:09.743,000] <inf> hace_global: HACE_STS: 0 [00:00:09.743,000] <err> hace_global: HACE poll timeout [00:00:09.743,000] <err> crypto: CBC mode ENCRYPT - Failed [00:00:09.743,000] <inf> hace_global: aspeed_crypto_session_free uart:~$ After: uart:~$ hash test sha256_test tv[0]:PASS tv[1]:PASS tv[2]:PASS tv[3]:PASS tv[4]:PASS sha384_test tv[0]:PASS tv[1]:PASS tv[2]:PASS tv[3]:PASS tv[4]:PASS tv[5]:PASS sha512_test tv[0]:PASS tv[1]:PASS tv[2]:PASS tv[3]:PASS tv[4]:PASS tv[5]:PASS uart:~$ crypto aes256_cbc_vault aes256_cbc vault key 1 Was waiting for: 6b c1 be e2 2e 40 9f 96 e9 3d 7e 11 73 93 17 2a ae 2d 8a 57 1e 03 ac 9c 9e b7 6f ac 45 af 8e 51 30 c8 1c 46 a3 5c e4 11 e5 fb c1 19 1a 0a 52 ef f6 9f 24 45 df 4f 9b 17 ad 2b 41 7b e6 6c 37 10 But got: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [00:00:05.771,000] <inf> hace_global: aspeed_crypto_session_setup [00:00:05.772,000] <inf> hace_global: data->cmd: 1c2098 [00:00:05.772,000] <inf> hace_global: crypto_data_src: 93340 [00:00:05.772,000] <inf> hace_global: crypto_data_dst: 93348 [00:00:05.772,000] <inf> hace_global: crypto_ctx_base: 93300 [00:00:05.772,000] <inf> hace_global: crypto_data_len: 80000040 [00:00:05.772,000] <inf> hace_global: crypto_cmd_reg: 11c2098 [00:00:05.772,000] <inf> hace_global: HACE_STS: 1000 [00:00:05.772,000] <inf> crypto: Output length (encryption): 80 [00:00:05.772,000] <inf> hace_global: aspeed_crypto_session_free [00:00:05.772,000] <inf> hace_global: aspeed_crypto_session_setup [00:00:05.772,000] <inf> hace_global: data->cmd: 1c2018 [00:00:05.772,000] <inf> hace_global: crypto_data_src: 93340 [00:00:05.772,000] <inf> hace_global: crypto_data_dst: 93348 [00:00:05.772,000] <inf> hace_global: crypto_ctx_base: 93300 [00:00:05.772,000] <inf> hace_global: crypto_data_len: 80000040 [00:00:05.772,000] <inf> hace_global: crypto_cmd_reg: 11c2018 [00:00:05.772,000] <inf> hace_global: HACE_STS: 1000 [00:00:05.772,000] <inf> crypto: Output length (decryption): 64 [00:00:05.772,000] <err> crypto: CBC mode DECRYPT - Mismatch between plaintext and decrypted cipher text [00:00:05.774,000] <inf> hace_global: aspeed_crypto_session_free uart:~$ Reviewed-by: Peter Delevoryas <peter@pjd.dev> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/arm/aspeed_ast10x0: Map the secure SRAMPhilippe Mathieu-Daudé1-1/+10
Some SRAM appears to be used by the Secure Boot unit and crypto accelerators. Name it 'secure sram'. Note, the SRAM base address was already present but unused (the 'SBC' index is used for the MMIO peripheral). Interestingly using CFLAGS=-Winitializer-overrides reports: ../hw/arm/aspeed_ast10x0.c:32:30: warning: initializer overrides prior initialization of this subobject [-Winitializer-overrides] [ASPEED_DEV_SBC] = 0x7E6F2000, ^~~~~~~~~~ ../hw/arm/aspeed_ast10x0.c:24:30: note: previous initialization is here [ASPEED_DEV_SBC] = 0x79000000, ^~~~~~~~~~ This fixes with Zephyr: uart:~$ rsa test rsa test vector[0]: [00:00:26.156,000] <err> os: ***** BUS FAULT ***** [00:00:26.157,000] <err> os: Precise data bus error [00:00:26.157,000] <err> os: BFAR Address: 0x79000000 [00:00:26.158,000] <err> os: r0/a1: 0x79000000 r1/a2: 0x00000000 r2/a3: 0x00001800 [00:00:26.158,000] <err> os: r3/a4: 0x79001800 r12/ip: 0x00000800 r14/lr: 0x0001098d [00:00:26.158,000] <err> os: xpsr: 0x81000000 [00:00:26.158,000] <err> os: Faulting instruction address (r15/pc): 0x0001e1bc [00:00:26.158,000] <err> os: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0 [00:00:26.158,000] <err> os: Current thread: 0x38248 (shell_uart) [00:00:26.165,000] <err> os: Halting system Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Delevoryas <peter@pjd.dev> [ clg: Fixed size of Secure Boot Controller Memory ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/arm/aspeed_ast10x0: Map I3C peripheralPhilippe Mathieu-Daudé1-0/+16
Since I don't have access to the datasheet, the relevant values were found in: https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi Reviewed-by: Peter Delevoryas <peter@pjd.dev> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/arm/aspeed_ast10x0: Add various unimplemented peripheralsPhilippe Mathieu-Daudé1-0/+35
Based on booting Zephyr demo from [1] running QEMU with '-d unimp' and checking missing devices in [2]. [1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07 [2] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/misc/aspeed_hace: Do not crash if address_space_map() failedPhilippe Mathieu-Daudé1-6/+15
address_space_map() can fail: uart:~$ hash test sha256_test tv[0]: Segmentation fault: 11 Thread 3 "qemu-system-arm" received signal SIGSEGV, Segmentation fault. gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0) at ../hw/misc/aspeed_hace.c:171 171 if (has_padding(s, &iov[id], *req_len, &total_msg_len, &pad_offset)) { (gdb) bt #0 gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0) at ../hw/misc/aspeed_hace.c:171 #1 do_hash_operation (s=s@entry=0x555556ce0bd0, algo=3, sg_mode=sg_mode@entry=true, acc_mode=acc_mode@entry=true) at ../hw/misc/aspeed_hace.c:224 #2 0x00005555559bdbb8 in aspeed_hace_write (opaque=<optimized out>, addr=12, data=262488, size=<optimized out>) at ../hw/misc/aspeed_hace.c:358 This change doesn't fix much, but at least the guest can't crash QEMU anymore. Instead it is still usable: uart:~$ hash test sha256_test tv[0]:hash_final error sha384_test tv[0]:hash_final error sha512_test tv[0]:hash_final error [00:00:06.278,000] <err> hace_global: HACE poll timeout [00:00:09.324,000] <err> hace_global: HACE poll timeout [00:00:12.261,000] <err> hace_global: HACE poll timeout uart:~$ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP levelPhilippe Mathieu-Daudé1-0/+13
Add more Aspeed watchdog registers from [*]. Since guests can righteously access them, log the access at 'unimplemented' level instead of 'guest-errors'. [*] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/drivers/watchdog/wdt_aspeed.c#L31 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Delevoryas <peter@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registersPhilippe Mathieu-Daudé1-1/+2
When booting the Zephyr demo in [1] we get: aspeed.io: unimplemented device write (size 4, offset 0x185128, value 0x030f1ff1) <-- aspeed.io: unimplemented device write (size 4, offset 0x18512c, value 0x03fffff1) This corresponds to this Zephyr code [2]: static int aspeed_wdt_init(const struct device *dev) { const struct aspeed_wdt_config *config = dev->config; struct aspeed_wdt_data *const data = dev->data; uint32_t reg_val; /* disable WDT by default */ reg_val = sys_read32(config->ctrl_base + WDT_CTRL_REG); reg_val &= ~WDT_CTRL_ENABLE; sys_write32(reg_val, config->ctrl_base + WDT_CTRL_REG); sys_write32(data->rst_mask1, config->ctrl_base + WDT_SW_RESET_MASK1_REG); <------ sys_write32(data->rst_mask2, config->ctrl_base + WDT_SW_RESET_MASK2_REG); return 0; } The register definitions are [3]: #define WDT_RELOAD_VAL_REG 0x0004 #define WDT_RESTART_REG 0x0008 #define WDT_CTRL_REG 0x000C #define WDT_TIMEOUT_STATUS_REG 0x0010 #define WDT_TIMEOUT_STATUS_CLR_REG 0x0014 #define WDT_RESET_MASK1_REG 0x001C #define WDT_RESET_MASK2_REG 0x0020 #define WDT_SW_RESET_MASK1_REG 0x0028 <------ #define WDT_SW_RESET_MASK2_REG 0x002C #define WDT_SW_RESET_CTRL_REG 0x0024 Currently QEMU only cover a MMIO region of size 0x20: #define ASPEED_WDT_REGS_MAX (0x20 / 4) Change to map the whole 'iosize' which might be bigger, covering the other registers. The MemoryRegionOps read/write handlers will report the accesses as out-of-bounds guest-errors, but the next commit will report them as unimplemented. [1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07 [2] https://github.com/AspeedTech-BMC/zephyr/commit/2e99f10ac27b [3] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/drivers/watchdog/wdt_aspeed.c#L31 Reviewed-by: Peter Delevoryas <peter@pjd.dev> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize'Philippe Mathieu-Daudé4-10/+10
Avoid confusing two different things: - the WDT I/O region size ('iosize') - at which offset the SoC map the WDT ('offset') While it is often the same, we can map smaller region sizes at larger offsets. Here we are interested in the I/O region size, so rename as 'iosize'. Reviewed-by: Peter Delevoryas <peter@pjd.dev> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> [ clg: Introduced temporary wdt_offset variable ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/nvram/eeprom_at24c: Make reset behavior more like hardwarePeter Delevoryas1-12/+10
EEPROM's are a form of non-volatile memory. After power-cycling an EEPROM, I would expect the I2C state machine to be reset to default values, but I wouldn't really expect the memory to change at all. The current implementation of the at24c EEPROM resets its internal memory on reset. This matches the specification in docs/devel/reset.rst: Cold reset is supported by every resettable object. In QEMU, it means we reset to the initial state corresponding to the start of QEMU; this might differ from what is a real hardware cold reset. It differs from other resets (like warm or bus resets) which may keep certain parts untouched. But differs from my intuition. For example, if someone writes some information to an EEPROM, then AC power cycles their board, they would expect the EEPROM to retain that information. It's very useful to be able to test things like this in QEMU as well, to verify software instrumentation like determining the cause of a reboot. Fixes: 5d8424dbd3e8 ("nvram: add AT24Cx i2c eeprom") Signed-off-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Corey Minyard <cminyard@mvista.com> Link: https://lore.kernel.org/r/20230128060543.95582-6-peter@pjd.dev Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/arm/aspeed: Add aspeed_eeprom.cPeter Delevoryas4-3/+109
- Create aspeed_eeprom.c and aspeed_eeprom.h - Include aspeed_eeprom.c in CONFIG_ASPEED meson source files - Include aspeed_eeprom.h in aspeed.c - Add fby35_bmc_fruid data - Use new at24c_eeprom_init_rom helper to initialize BMC FRUID EEPROM with data from aspeed_eeprom.c wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd qemu-system-aarch64 -machine fby35-bmc -nographic -mtdblock fby35.mtd ... user: root pass: 0penBmc ... root@bmc-oob:~# fruid-util bb FRU Information : Baseboard --------------- : ------------------ Chassis Type : Rack Mount Chassis Chassis Part Number : N/A Chassis Serial Number : N/A Board Mfg Date : Fri Jan 7 10:30:00 2022 Board Mfg : XXXXXX Board Product : Management Board wBMC Board Serial : XXXXXXXXXXXXX Board Part Number : XXXXXXXXXXXXXX Board FRU ID : 1.0 Board Custom Data 1 : XXXXXXXXX Board Custom Data 2 : XXXXXXXXXXXXXXXXXX Product Manufacturer : XXXXXX Product Name : Yosemite V3.5 EVT2 Product Part Number : XXXXXXXXXXXXXX Product Version : EVT2 Product Serial : XXXXXXXXXXXXX Product Asset Tag : XXXXXXX Product FRU ID : 1.0 Product Custom Data 1 : XXXXXXXXX Product Custom Data 2 : N/A root@bmc-oob:~# fruid-util bmc FRU Information : BMC --------------- : ------------------ Board Mfg Date : Mon Jan 10 21:42:00 2022 Board Mfg : XXXXXX Board Product : BMC Storage Module Board Serial : XXXXXXXXXXXXX Board Part Number : XXXXXXXXXXXXXX Board FRU ID : 1.0 Board Custom Data 1 : XXXXXXXXX Board Custom Data 2 : XXXXXXXXXXXXXXXXXX Product Manufacturer : XXXXXX Product Name : Yosemite V3.5 EVT2 Product Part Number : XXXXXXXXXXXXXX Product Version : EVT2 Product Serial : XXXXXXXXXXXXX Product Asset Tag : XXXXXXX Product FRU ID : 1.0 Product Custom Data 1 : XXXXXXXXX Product Custom Data 2 : Config A root@bmc-oob:~# fruid-util nic FRU Information : NIC --------------- : ------------------ Board Mfg Date : Tue Nov 2 08:51:00 2021 Board Mfg : XXXXXXXX Board Product : Mellanox ConnectX-6 DX OCP3.0 Board Serial : XXXXXXXXXXXXXXXXXXXXXXXX Board Part Number : XXXXXXXXXXXXXXXXXXXXX Board FRU ID : FRU Ver 0.02 Product Manufacturer : XXXXXXXX Product Name : Mellanox ConnectX-6 DX OCP3.0 Product Part Number : XXXXXXXXXXXXXXXXXXXXX Product Version : A9 Product Serial : XXXXXXXXXXXXXXXXXXXXXXXX Product Custom Data 3 : ConnectX-6 DX Signed-off-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Corey Minyard <cminyard@mvista.com> Link: https://lore.kernel.org/r/20230128060543.95582-5-peter@pjd.dev Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/nvram/eeprom_at24c: Add init_rom field and at24c_eeprom_init_rom helperPeter Delevoryas1-5/+31
Allows users to specify binary data to initialize an EEPROM, allowing users to emulate data programmed at manufacturing time. - Added init_rom and init_rom_size attributes to TYPE_AT24C_EE - Added at24c_eeprom_init_rom helper function to initialize attributes - If -drive property is provided, it overrides init_rom data Signed-off-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Ninad Palsule <ninadpalsule@us.ibm.com> Link: https://lore.kernel.org/r/20230128060543.95582-4-peter@pjd.dev Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/arm/aspeed: Replace aspeed_eeprom_init with at24c_eeprom_initPeter Delevoryas1-52/+43
aspeed_eeprom_init is an exact copy of at24c_eeprom_init, not needed. Signed-off-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Corey Minyard <cminyard@mvista.com> Link: https://lore.kernel.org/r/20230128060543.95582-3-peter@pjd.dev Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boardsPeter Delevoryas3-24/+18
This helper is useful in board initialization because lets users initialize and realize an EEPROM on an I2C bus with a single function call. Signed-off-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Corey Minyard <cminyard@mvista.com> Link: https://lore.kernel.org/r/20230128060543.95582-2-peter@pjd.dev Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07m25p80: Add the is25wp256 SFPD tableGuenter Roeck3-1/+44
Generated from hardware using the following command and then padding with 0xff to fill out a power-of-2: xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp Cc: Michael Walle <michael@walle.cc> Cc: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20221221122213.1458540-1-linux@roeck-us.net> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/net: Fix read of uninitialized memory in ftgmac100Stephen Longfield1-2/+2
With the `size += 4` before the call to `crc32`, the CRC calculation would overrun the buffer. Size is used in the while loop starting on line 1009 to determine how much data to write back, with the last four bytes coming from `crc_ptr`, so do need to increase it, but should do this after the computation. I'm unsure why this use of uninitialized memory in the CRC doesn't result in CRC errors, but it seems clear to me that it should not be included in the calculation. Signed-off-by: Stephen Longfield <slongfield@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20221220221437.3303721-1-slongfield@google.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07aspeed: Add Supermicro X11 SPI machine typeGuenter Roeck1-0/+33
supermicrox11-bmc is configured with ast2400-a1 SoC. This does not match the Supermicro documentation for X11 BMCs, and it does not match the devicetree file in the Linux kernel. As it turns out, some Supermicro X11 motherboards use AST2400 SoCs, while others use AST2500. Introduce new machine type supermicrox11-spi-bmc with AST2500 SoC to match the devicetree description in the Linux kernel. Hardware configuration details for this machine type are guesswork and taken from defaults as well as from the Linux kernel devicetree file. The new machine type was tested with aspeed-bmc-supermicro-x11spi.dts from the Linux kernel and with Linux versions 6.0.3 and 6.1-rc2. Linux booted successfully from initrd and from both SPI interfaces. Ethernet interfaces were confirmed to be operational. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20221025165109.1226001-1-linux@roeck-us.net [ clg: Renamed machine to 'supermicro-x11spi-bmc' ] Message-Id: <20221025165109.1226001-1-linux@roeck-us.net> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07tests/avocado: Truncate M2S-FG484 SOM SPI flash to 16MiBPhilippe Mathieu-Daudé1-1/+4
The M2S-FG484 SOM uses a 16 MiB SPI flash (Spansion S25FL128SDPBHICO). Since the test asset is bigger, truncate it to the correct size to avoid when running the test_arm_emcraft_sf2 test: qemu-system-arm: device requires 16777216 bytes, block backend provides 67108864 bytes Add comment regarding the M2S-FG484 SOM hardware in hw/arm/msf2-som.c. Reported-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-02-07hw/riscv: virt: Simplify virt_{get,set}_aclint()Bin Meng1-4/+2
There is no need to declare an intermediate "MachineState *ms". Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230206085007.3618715-1-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza5-16/+31
As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a mem_size (which is defaulted to MachineState::ram_size in all boards) and the FDT pointer. And it makes a very important assumption: the DRAM interval dram_base + mem_size is contiguous. This is indeed the case for most boards that use a FDT. The Icicle Kit board works with 2 distinct RAM banks that are separated by a gap. We have a lower bank with 1GiB size, a gap follows, then at 64GiB the high memory starts. MachineClass::default_ram_size for this board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM size, meaning that there we'll always have at least 512 MiB in the Hi RAM area. Using riscv_compute_fdt_addr() in this board is weird because not only the board has sparse RAM, and it's calling it using the base address of the Lo RAM area, but it's also using a mem_size that we have guarantees that it will go up to the Hi RAM. All the function assumptions doesn't work for this board. In fact, what makes the function works at all in this case is a coincidence. Commit 1a475d39ef54 introduced a 3GB boundary for the FDT, down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x80000000 (2 Gb) and it has a 1Gb size, so it will fall in the conditions to put the FDT under a 3Gb address, which happens to be exactly at the end of DRAM_LO. If the base address of the Lo area started later than 3Gb this function would be unusable by the board. Changing any assumptions inside riscv_compute_fdt_addr() can also break it by accident as well. Let's change riscv_compute_fdt_addr() semantics to be appropriate to the Icicle Kit board and for future boards that might have sparse RAM topologies to worry about: - relieve the condition that the dram_base + mem_size area is contiguous, since this is already not the case today; - receive an extra 'dram_size' size attribute that refers to a contiguous RAM block that the board wants the FDT to reside on. Together with 'mem_size' and 'fdt', which are now now being consumed by a MachineState pointer, we're able to make clear assumptions based on the DRAM block and total mem_size available to ensure that the FDT will be put in a valid RAM address. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230201171212.1219375-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza5-16/+40
A common trend in other archs is to calculate the fdt address, which is usually straightforward, and then calling a function that loads the fdt/dtb by using that address. riscv_load_fdt() is doing a bit too much in comparison. It's calculating the fdt address via an elaborated heuristic to put the FDT at the bottom of DRAM, and "bottom of DRAM" will vary across boards and configurations, then it's actually loading the fdt, and finally it's returning the fdt address used to the caller. Reduce the existing complexity of riscv_load_fdt() by splitting its code into a new function, riscv_compute_fdt_addr(), that will take care of all fdt address logic. riscv_load_fdt() can then be a simple function that just loads a fdt at the given fdt address. We're also taken the opportunity to clarify the intentions and assumptions made by these functions. riscv_load_fdt() is now receiving a hwaddr as fdt_addr because there is no restriction of having to load the fdt in higher addresses that doesn't fit in an uint32_t. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230201171212.1219375-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07hw/riscv/boot.c: calculate fdt size after fdt_pack()Daniel Henrique Barboza1-4/+6
fdt_pack() can change the fdt size, meaning that fdt_totalsize() can contain a now deprecated (bigger) value. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230201171212.1219375-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'Daniel Henrique Barboza1-9/+9
Follow the QEMU convention of naming MachineState pointers as 'ms' by renaming the instances where we're calling it 'mc'. Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230124212234.412630-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms'Daniel Henrique Barboza1-217/+217
We have a convention in other QEMU boards/archs to name MachineState pointers as either 'machine' or 'ms'. MachineClass pointers are usually called 'mc'. The 'virt' RISC-V machine has a lot of instances where MachineState pointers are named 'mc'. There is nothing wrong with that, but we gain more compatibility with the rest of the QEMU code base, and easier reviews, if we follow QEMU conventions. Rename all 'mc' MachineState pointers to 'ms'. This is a very tedious and mechanical patch that was produced by doing the following: - find/replace all 'MachineState *mc' to 'MachineState *ms'; - find/replace all 'mc->fdt' to 'ms->fdt'; - find/replace all 'mc->smp.cpus' to 'ms->smp.cpus'; - replace any remaining occurrences of 'mc' that the compiler complained about. Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230124212234.412630-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07hw/riscv/virt.c: calculate socket count once in create_fdt_imsic()Daniel Henrique Barboza1-15/+19
riscv_socket_count() returns either ms->numa_state->num_nodes or 1 depending on NUMA support. In any case the value can be retrieved only once and used in the rest of the function. This will also alleviate the rename we're going to do next by reducing the instances of MachineState 'mc' inside hw/riscv/virt.c. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230124212234.412630-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07hw/riscv: boot: Don't use CSRs if they are disabledAlistair Francis1-0/+9
If the CSRs and CSR instructions are disabled because the Zicsr extension isn't enabled then we want to make sure we don't run any CSR instructions in the boot ROM. This patches removes the CSR instructions from the reset-vec if the extension isn't enabled. We replace the instruction with a NOP instead. Note that we don't do this for the SiFive U machine, as we are modelling the hardware in that case. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07include/hw/riscv/opentitan: update opentitan IRQsWilfred Mallawa1-40/+40
Updates the opentitan IRQs to match the latest supported commit of Opentitan from TockOS. OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47 Memory layout as per [1] [1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230123063619.222459-1-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-06virtio-mem: Proper support for preallocation with migrationDavid Hildenbrand1-0/+87
Ordinary memory preallocation runs when QEMU starts up and creates the memory backends, before processing the incoming migration stream. With virtio-mem, we don't know which memory blocks to preallocate before migration started. Now that we migrate the virtio-mem bitmap early, before migrating any RAM content, we can safely preallocate memory for all plugged memory blocks before migrating any RAM content. This is especially relevant for the following cases: (1) User errors With hugetlb/files, if we don't have sufficient backend memory available on the migration destination, we'll crash QEMU (SIGBUS) during RAM migration when running out of backend memory. Preallocating memory before actual RAM migration allows for failing gracefully and informing the user about the setup problem. (2) Excluded memory ranges during migration For example, virtio-balloon free page hinting will exclude some pages from getting migrated. In that case, we won't crash during RAM migration, but later, when running the VM on the destination, which is bad. To fix this for new QEMU machines that migrate the bitmap early, preallocate the memory early, before any RAM migration. Warn with old QEMU machines. Getting postcopy right is a bit tricky, but we essentially now implement the same (problematic) preallocation logic as ordinary preallocation: preallocate memory early and discard it again before precopy starts. During ordinary preallocation, discarding of RAM happens when postcopy is advised. As the state (bitmap) is loaded after postcopy was advised but before postcopy starts listening, we have to discard memory we preallocated immediately again ourselves. Note that nothing (not even hugetlb reservations) guarantees for postcopy that backend memory (especially, hugetlb pages) are still free after they were freed ones while discarding RAM. Still, allocating that memory at least once helps catching some basic setup problems. Before this change, trying to restore a VM when insufficient hugetlb pages are around results in the process crashing to to a "Bus error" (SIGBUS). With this change, QEMU fails gracefully: qemu-system-x86_64: qemu_prealloc_mem: preallocating memory failed: Bad address qemu-system-x86_64: error while loading state for instance 0x0 of device '0000:00:03.0/virtio-mem-device-early' qemu-system-x86_64: load of migration failed: Cannot allocate memory And we can even introspect the early migration data, including the bitmap: $ ./scripts/analyze-migration.py -f STATEFILE { "ram (2)": { "section sizes": { "0000:00:03.0/mem0": "0x0000000780000000", "0000:00:04.0/mem1": "0x0000000780000000", "pc.ram": "0x0000000100000000", "/rom@etc/acpi/tables": "0x0000000000020000", "pc.bios": "0x0000000000040000", "0000:00:02.0/e1000.rom": "0x0000000000040000", "pc.rom": "0x0000000000020000", "/rom@etc/table-loader": "0x0000000000001000", "/rom@etc/acpi/rsdp": "0x0000000000001000" } }, "0000:00:03.0/virtio-mem-device-early (51)": { "tmp": "00 00 00 01 40 00 00 00 00 00 00 07 80 00 00 00 00 00 00 00 00 20 00 00 00 00 00 00", "size": "0x0000000040000000", "bitmap": "ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff [...] }, "0000:00:04.0/virtio-mem-device-early (53)": { "tmp": "00 00 00 08 c0 00 00 00 00 00 00 07 80 00 00 00 00 00 00 00 00 20 00 00 00 00 00 00", "size": "0x00000001fa400000", "bitmap": "ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff [...] }, [...] Reported-by: Jing Qi <jinqi@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com>S Signed-off-by: David Hildenbrand <david@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2023-02-06virtio-mem: Migrate immutable properties earlyDavid Hildenbrand2-3/+52
The bitmap and the size are immutable while migration is active: see virtio_mem_is_busy(). We can migrate this information early, before migrating any actual RAM content. Further, all information we need for sanity checks is immutable as well. Having this information in place early will, for example, allow for properly preallocating memory before touching these memory locations during RAM migration: this way, we can make sure that all memory was actually preallocated and that any user errors (e.g., insufficient hugetlb pages) can be handled gracefully. In contrast, usable_region_size and requested_size can theoretically still be modified on the source while the VM is running. Keep migrating these properties the usual, late, way. Use a new device property to keep behavior of compat machines unmodified. Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com>S Signed-off-by: David Hildenbrand <david@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2023-02-06virtio-mem: Fail if a memory backend with "prealloc=on" is specifiedDavid Hildenbrand1-0/+6
"prealloc=on" for the memory backend does not work as expected, as virtio-mem will simply discard all preallocated memory immediately again. In the best case, it's an expensive NOP. In the worst case, it's an unexpected allocation error. Instead, "prealloc=on" should be specified for the virtio-mem device only, such that virtio-mem will try preallocating memory before plugging memory dynamically to the guest. Fail if such a memory backend is provided. Tested-by: Michal Privoznik <mprivozn@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com>S Signed-off-by: David Hildenbrand <david@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2023-02-06migration: Remove unused threshold_size parameterJuan Quintela2-2/+1
Until previous commit, save_live_pending() was used for ram. Now with the split into state_pending_estimate() and state_pending_exact() it is not needed anymore, so remove them. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2023-02-06migration: Split save_live_pending() into state_pending_*Juan Quintela3-16/+18
We split the function into to: - state_pending_estimate: We estimate the remaining state size without stopping the machine. - state pending_exact: We calculate the exact amount of remaining state. The only "device" that implements different functions for _estimate() and _exact() is ram. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2023-02-06migration: No save_live_pending() method uses the QEMUFile parameterJuan Quintela2-2/+2
So remove it everywhere. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2023-02-06mac_oldworld: Allow specifying nvram backing storeBALATON Zoltan1-1/+7
Add a way to set a backing store for the mac_nvram. Use -drive file=nvram.img,format=raw,if=mtd to specify backing file where nvram.img must be MACIO_NVRAM_SIZE which is 8192 bytes. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <1aadee8f0ca0f56cf1b7c45c3944676a07d91de9.1675297286.git.balaton@eik.bme.hu> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2023-02-06mac_nvram: Add block backend to persist NVRAM contentsBALATON Zoltan1-0/+28
Add a way to set a backing store for the mac_nvram similar to what spapr_nvram or mac_via PRAM already does to allow to save its contents between runs. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <4b1605a9e484cc95f6e141f297487a070fd418ac.1675297286.git.balaton@eik.bme.hu> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2023-02-06hw/misc/macio: Return bool from functions taking errpBALATON Zoltan1-37/+25
Use the convention to return bool from functions which take an error pointer which allows for callers to pass through their error pointer without needing a local. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <bfce0751e82b031f5e6fb3c32cfbce6325434400.1674001242.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2023-02-06hw/misc/macio: Remove some single use local variablesBALATON Zoltan1-8/+5
Drop some local variables that could just be substituted at the single place they were used. This makes the code shorter and simpler. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <165a4ea190af7c09832f50f02004fad82f704898.1674001242.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2023-02-06hw/misc/macio: Rename sysbus_dev to sbd for consistency and brevityBALATON Zoltan1-43/+35
Some functions use sysbus_dev while others sbd name for local variable storing a sysbus device pointer. Standardise on the shorter name to be consistent and make the code easier to read as short name is less distracting and needs less line breaks. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <6c79d6903fc11e153f8050a374904c2b5d5db585.1674001242.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2023-02-06hw/misc/macio: Avoid some QOM castsBALATON Zoltan1-7/+7
At several places we already have the object pointer with the right type so we don't need to cast it back and forth. Avoiding these casts improves readability. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <67b2d4700879c3b4cd574f1faa1a0d1950b3d0ee.1674001242.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2023-02-06mac_{old,new}world: Use local variable instead of qdev_get_machine()BALATON Zoltan2-4/+2
We already have machine in a local variable so no need to use qdev_get_machine(), also remove now unneeded line break. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <719299533b89aa4516966065eae05c75744f50d3.1672868854.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2023-02-06input/adb: Only include header where neededBALATON Zoltan3-6/+0
The header hw/input/adb.h is included by some files that don't need it. Clean it up and include only where necessary. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <f46bc751e8426f9d937c9540f2e67d2f0b2cc582.1672868854.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2023-02-05hw/display/sm501: Code style fixBALATON Zoltan1-1/+2
Fix checkpatch warning about multi-line comment. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <8801292992a304609e1eac680fe36b515592b926.1674333199.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-02-05hw/display/sm501: Remove unneeded casts from void pointerBALATON Zoltan1-11/+11
This is not needed in C. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <58f599387dd0739ea1880bfb678872c0be26bf1b.1674333199.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-02-05hw/display/sm501: Remove parenthesis around constant macro definitionsBALATON Zoltan1-197/+197
No need to wrap constants in parenthesis. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <9194546b73b05e7098761ec62b2dfd0699b97b65.1674333199.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-02-05hw/ppc/pegasos2: Fix a typo in a commentBALATON Zoltan1-1/+1
Reported-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230203194312.33834745712@zero.eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-02-05ppc/pnv/pci: Fix PHB xscom registers memory region nameFrederic Barrat1-1/+1
The name is for the region mapping the PHB xscom registers. It was apparently a bad cut-and-paste from the per-stack pci xscom area just above, so we had two regions with the same name. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20230127122848.550083-5-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
generated by cgit v1.1 at 2025-01-27 05:16:48 +0000