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2013-12-13Merge remote-tracking branch 'bonzini/virtio' into stagingAnthony Liguori17-320/+387
# By Andreas Färber (18) and Paolo Bonzini (12) # Via Paolo Bonzini * bonzini/virtio: (30 commits) virtio: Convert exit to unrealize virtio: Complete converting VirtioDevice to QOM realize virtio-scsi: Convert to QOM realize virtio-rng: Convert to QOM realize virtio-balloon: Convert to QOM realize virtio-net: Convert to QOM realize virtio-serial: Convert to QOM realize virtio-blk: Convert to QOM realize virtio-9p: Convert to QOM realize virtio: Start converting VirtioDevice to QOM realize virtio-scsi: QOM realize preparations virtio-rng: QOM realize preparations virtio-balloon: QOM realize preparations virtio-net: QOM realize preparations virtio-serial: QOM realize preparations virtio-blk: QOM realize preparations virtio-9p: QOM realize preparations virtio-blk-dataplane: Improve error reporting virtio-pci: add device_unplugged callback virtio-rng: switch exit callback to VirtioDeviceClass ...
2013-12-13Merge remote-tracking branch 'mst/tags/for_anthony' into stagingAnthony Liguori15-91/+135
acpi.pci,pc,memory core fixes Most notably this includes changes to exec to support full 64 bit addresses. This also flushes out patches that got queued during 1.7 freeze. There are new tests, and a bunch of bug fixes all over the place. There are also some changes mostly useful for downstreams. I'm also listing myself as pc co-maintainer. I'm doing this reluctantly, but this seems to be necessary to make sure patches are not lost or delayed too much, and posting the MAINTAINERS patch did not seem to make anyone else volunteer. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed 11 Dec 2013 10:21:51 AM PST using RSA key ID D28D5469 # gpg: Can't check signature: public key not found # By Michael S. Tsirkin (14) and others # Via Michael S. Tsirkin * mst/tags/for_anthony: (28 commits) pc: use macro for HPET type hpet: fix build with CONFIG_HPET off acpi unit-test: adjust the test data structure for better handling acpi unit-test: load and check facs table exec: separate sections and nodes per address space memory.c: bugfix - ref counting mismatch in memory_region_find hpet: enable to entitle more irq pins for hpet hpet: inverse polarity when pin above ISA_NUM_IRQS pci: fix pci bridge fw path ACPI DSDT: Make control method `IQCR` serialized acpi: strip compiler info in built-in DSDT acpi unit-test: verify signature and checksum smbios: Set system manufacturer, product & version by default exec: reduce L2_PAGE_SIZE exec: make address spaces 64-bit wide exec: memory radix tree page level compression exec: pass hw address to phys_page_find exec: extend skip field to 6 bit, page entry to 32 bit exec: replace leaf with skip split definitions for exec.c and translate-all.c radix trees ... Message-id: cover.1386786228.git.mst@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-12-13Merge remote-tracking branch 'bonzini/scsi-next' into stagingAnthony Liguori2-9/+34
# By Paolo Bonzini (4) and Peter Lieven (1) # Via Paolo Bonzini * bonzini/scsi-next: help: add id suboption to -iscsi scsi-disk: fix WRITE SAME with large non-zero payload block/iscsi: introduce bdrv_co_{readv, writev, flush_to_disk} scsi-disk: fix VERIFY emulation scsi-bus: fix transfer length and direction for VERIFY command Message-id: 1386594157-17535-1-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-12-11pc: use macro for HPET typeMichael S. Tsirkin1-1/+1
avoid hard-coding strings Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-11hpet: fix build with CONFIG_HPET offMichael S. Tsirkin1-6/+0
make hpet_find inline so we don't need to build hpet.c to check if hpet is enabled. Fixes link error with CONFIG_HPET off. Cc: qemu-stable@nongnu.org Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-11hpet: enable to entitle more irq pins for hpetLiu Ping Fan4-10/+33
Owning to some different hardware design, piix and q35 need different compat. So making them diverge. On q35, IRQ2/8 can be reserved for hpet timer 0/1. And pin 16~23 can be assigned to hpet as guest chooses. So we introduce intcap property to do that. Consider the compat and piix/q35, we finally have the following value for intcap: For piix, hpet's intcap is hard coded as IRQ2. For pc-q35-1.7 and earlier, we use IRQ2 for compat reason. Otherwise IRQ2, IRQ8, and IRQ16~23 are allowed. Signed-off-by: Liu Ping Fan <pingfank@linux.vnet.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-11hpet: inverse polarity when pin above ISA_NUM_IRQSLiu Ping Fan1-2/+12
According to hpet spec, hpet irq is high active. But according to ICH spec, there is inversion before the input of ioapic. So the OS will expect low active on this IRQ line. (On bare metal, if OS driver claims high active on this line, spurious irq is generated) We fold the emulation of this inversion inside the hpet logic. Signed-off-by: Liu Ping Fan <pingfank@linux.vnet.ibm.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-11pci: fix pci bridge fw pathGerd Hoffmann1-1/+1
qemu uses "pci" as name for pci bridges in the firmware device path. seabios expects "pci-bridge". Result is that bootorder is broken for devices behind pci bridges. Some googling suggests that "pci-bridge" is the correct one. At least PPC-based Apple machines are using this. See question "How do I boot from a device attached to a PCI card" here: http://www.netbsd.org/ports/macppc/faq.html So lets change qemu to use "pci-bridge" too. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10Merge remote-tracking branch 'stefanha/net-next' into stagingAnthony Liguori1-15/+20
# By Vincenzo Maffione (2) and others # Via Stefan Hajnoczi * stefanha/net-next: net: Update netdev peer on link change virtio-net: don't update mac_table in error state MAINTAINERS: Add netmap maintainers net: Adding netmap network backend Message-id: 1386594692-21278-1-git-send-email-stefanha@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-12-10Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20131210' into ↵Anthony Liguori8-131/+1060
staging target-arm queue: * support REFCNT register on integrator/cp board * implement the A9MP's global timer * add the 'virt' platform * support '-cpu host' on KVM/ARM * Cadence GEM ethernet device bugfixes * Implement 32-bit ARMv8 VSEL, VMAXNM, VMINNM * fix TTBCR write masking * update 32 bit decoder to use new qemu_ld/st TCG opcodes # gpg: Signature made Tue 10 Dec 2013 06:22:01 AM PST using RSA key ID 14360CDE # gpg: Can't check signature: public key not found # By Peter Crosthwaite (16) and others # Via Peter Maydell * pmaydell/tags/pull-target-arm-20131210: (37 commits) target-arm: fix TTBCR write masking target-arm: Use new qemu_ld/st opcodes target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions. target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions. softfloat: Add minNum() and maxNum() functions to softfloat. softfloat: Remove unused argument from MINMAX macro. target-arm: Implement ARMv8 VSEL instruction. target-arm: Move call to disas_vfp_insn out of disas_coproc_insn. net/cadence_gem: Don't rx packets when no rx buffer available net/cadence_gem: Improve can_receive debug printfery net/cadence_gem: Fix register w1c logic net/cadence_gem: Fix small packet FCS stripping net/cadence_gem: Fix rx multi-fragment packets net/cadence_gem: Add missing VMSTATE_END_OF_LIST net/cadence_gem: Implement SAR (de)activation net/cadence_gem: Implement SAR match bit in rx desc net/cadence_gem: Implement RX descriptor match mode flags net/cadence_gem: Prefetch rx descriptors ASAP net/cadence_gem: simplify rx buf descriptor walking net/cadence_gem: Don't assert against 0 buffer address ... Message-id: 1386686613-2390-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-12-10Merge remote-tracking branch 'kraxel/tags/pull-audio-1' into stagingAnthony Liguori2-2/+3
Change audio wakeup rate from 250 Hz to 100 Hz. Emulation bugfixes for intel-hda and adlib. # gpg: Signature made Mon 09 Dec 2013 06:04:16 AM PST using RSA key ID D3E87138 # gpg: Can't check signature: public key not found # By Gerd Hoffmann (2) and others # Via Gerd Hoffmann * kraxel/tags/pull-audio-1: intel-hda: fix position buffer adlib: fix patching of port I/O addresses audio: adjust pulse to 100Hz wakeup rate audio: Lower default wakeup rate to 100 times / second Message-id: 1386597974-26506-1-git-send-email-kraxel@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-12-10net/cadence_gem: Don't rx packets when no rx buffer availablePeter Crosthwaite1-1/+10
Return false from can_receive() when no valid buffer descriptor is available. Ensures against mass packet droppage in some applications. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: cde00ef774e84e2586bf10fd37b542f75bf36cfb.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10net/cadence_gem: Improve can_receive debug printferyPeter Crosthwaite1-2/+10
Currently this just floods indicating that can_receive has been called by the net framework. Instead, save the result of the most recent can_receive callback as state and only print a message if the result changes (indicating some sort of actual state change in GEM). Make said debug message more meaningful as well. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 2eb74ca6a5756aea242d9f525961db95d6cfcf2c.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10net/cadence_gem: Fix register w1c logicPeter Crosthwaite1-7/+6
This write-1-clear logic was incorrect. It was always clearing w1c bits regardless of whether the written value was 1 or not. i.e. it was implementing a write-anything-to-clear strategy. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: ed905b04d3343966ded425f06aa2224bc7a35b59.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10net/cadence_gem: Fix small packet FCS strippingPeter Crosthwaite1-5/+8
The minimum packet size is 64, however this is before FCS stripping occurs. So when FCS stripping the minimum packet size is 60. Fix. Reported-by: Deepika Dhamija <deepika@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 8aac5bd737f9cf48b87f32943d7eb5939061e546.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10net/cadence_gem: Fix rx multi-fragment packetsPeter Crosthwaite1-1/+1
Bytes_to_copy was being updated before its final use where it advances the rx buffer pointer. This was causing total mayhem, where packet data for any subsequent fragments was being fetched from the wrong place. Reported-by: Deepika Dhamija <deepika@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: c2a1c65c1fd06eb274442a0fa4a6839d940e145e.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10net/cadence_gem: Add missing VMSTATE_END_OF_LISTPeter Crosthwaite1-0/+1
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 8f8c2bfb15f40fb5f0d5766aa4cd3d54c596de6a.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10net/cadence_gem: Implement SAR (de)activationPeter Crosthwaite1-4/+23
The Specific address registers can be enabled or disabled by software. QEMU was assuming they were always enabled. Implement the disable/enable feature. SARs are disabled by writing to the lower half register. They are re-enabled by then writing the upper half. Reported-by: Deepika Dhamija <deepika@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 49efd1f7450af8f980b967d3054245bae137866c.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10net/cadence_gem: Implement SAR match bit in rx descPeter Crosthwaite1-0/+2
Bit 27 of the RX buffer desc word 1 should be set when the packet was accepted due to specific address register match. Implement. This feature is absent from the Xilinx documentation (UG585) but the behaviour is tested as accurate on real hardware. Reported-by: Deepika Dhamija <deepika@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 7e3f26fc4ab244e8123efc12723e7164730abdcb.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10net/cadence_gem: Implement RX descriptor match mode flagsPeter Crosthwaite1-13/+69
The various Rx packet address matching mode flags were not being set in the rx descriptor. Implement. Reported-by: Deepika Dhamija <deepika@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 6002a24a6a8ceaa11d3009ab5392840d1c084b28.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10net/cadence_gem: Prefetch rx descriptors ASAPPeter Crosthwaite1-27/+35
The real hardware prefetches rx buffer descriptors ASAP and potentially throws relevant interrupts following the fetch even in the absence of a received packet. Reported-by: Deepika Dhamija <deepika@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 41629e35edfdb1f02f1e401f2c3d0e2e4c9e44b3.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10net/cadence_gem: simplify rx buf descriptor walkingPeter Crosthwaite1-28/+9
There was a replication of the rx descriptor address walking logic. Reorder the flow control to remove. This refactoring also obsoletes the local variables packet_desc_addr and last_desc_addr. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 2a425b457ff0b57274bf206ad2236690cd7f5909.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10net/cadence_gem: Don't assert against 0 buffer addressPeter Crosthwaite1-9/+0
This has no real hardware analog and asserting correctness of DMA addresses is not a perhiperal level problem. Delete. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: fc02417eb1874cb05e4f20531c6203c5a00110f1.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10net/cadence_gem: Update DMA rx descriptors as we process themEdgar E. Iglesias1-17/+16
We were updating the ownership bit of all descriptors if packets get split and written through several descriptors. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: d61b7847b51487118783c93765a485bc5c66d272.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10net/cadence_gem: Implement mac level loopback modePeter Crosthwaite1-1/+1
Cadence GEM has a MAC level loopback mode. Implement. Use the same basic operation as the already implemented PHY loopback. Reported-by: Deepika Dhamija <deepika@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 3a0baf1b6b2fc1be638bdf1a37408ec38988e970.1386136219.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10hw/arm/virt: Support -cpu hostPeter Maydell1-0/+8
Support -cpu host in virt machine (treating it like an A15, ie with a GIC v2 and the A15's private peripherals.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-12-git-send-email-peter.maydell@linaro.org
2013-12-10hw/arm: Add 'virt' platformPeter Maydell2-1/+445
Add 'virt' platform support corresponding to arch/arm/mach-virt in the Linux kernel tree. This has no platform-specific code but can use any device whose kernel driver is is able to work purely from a device tree node. We use this to instantiate a minimal set of devices: a GIC and some virtio-mmio transports. Signed-off-by: John Rigby <john.rigby@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-8-git-send-email-peter.maydell@linaro.org [PMM: Significantly overhauled: * renamed user-facing machine to just "virt" * removed the A9 support (it can't work since the A9 has no generic timers) * added virtio-mmio transports instead of random set of 'soc' devices (though we retain a pl011 UART) * instead of updating io_base as we step through adding devices, define a memory map with an array (similar to vexpress) * similarly, define irqmap with an array * folded in some minor fixes from John's aarch64-support patch * rather than explicitly doing endian-swapping on FDT cells, use fdt APIs that let us just pass in host-endian values and let the fdt layer take care of the swapping * miscellaneous minor code cleanups and style fixes ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10hw/arm/boot: Allow boards to provide an fdt blobJohn Rigby1-12/+20
If no fdt is provided on command line and the new field get_dtb in struct arm_boot_info is set then call it to get a device tree blob. Signed-off-by: John Rigby <john.rigby@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-4-git-send-email-peter.maydell@linaro.org [PMM: minor tweaks and cleanup] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10cpu/a9mpcore: Add Global TimerFrançois LEGAL1-5/+21
Add the global timer to A9 MPCore. Signed-off-by: François LEGAL <devel@thom.fr.eu.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: ff92f35f438ac671b57d99d823723dd3e62d2c49.1385969450.git.peter.crosthwaite@xilinx.com [PC Changes: * new commit message * split off original version as a separate patch * Rebased against new mpcore implementation (with struct embedding) ] Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10hw/timer: Introduce ARM A9 Global Timer.Peter Crosthwaite2-0/+370
The ARM A9 MPCore has a timer that is global to all cores in the cluster. The timer is shared but each core has a private independent comparator and interrupt. Based on version contributed by Francois LEGAL. Signed-off-by: François LEGAL <devel@thom.fr.eu.org> Message-id: 4918e89476b8da916be2964ec41578b50d569a37.1385969450.git.peter.crosthwaite@xilinx.com [PC changes: * New commit message * Re-implemented as single timer model * Fixed backwards counting issue in polled mode * completed VMSD fields * macroified magic numbers (and headerified reg definitions) * split of as device-model-only patch * use bitops for 64 bit register access * Fixed auto increment mode to check condition properly * general cleanup (names/style etc). ] Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [PMM: * minor typo fixes * added missing return after error_setg() * dropped setting dc->no_user = 1 ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10cpu/a9mpcore: reorder operations/declarationsPeter Crosthwaite1-14/+14
To make it consistent for easier code reading. The order in which variables are defined and functions are called is set to match the address map ordering. The new consistent order of doing stuff is: SCU -> GIC -> MPTimer -> WDT. 0 functional change. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 8f31398e6d9a93f57291399f269039da1a77a2b5.1385969450.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10cpu/a9mpcore: rename timerbusdev variablePeter Crosthwaite1-4/+4
Rename this variable for consistency with the above defined mptimerdev variable. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 28939ef95589a62414634e86c47cef76b21b15f7.1385969450.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10integrator/cp: add support for REFCNT registerJan Petrous1-3/+10
Linux kernel from version 3.4 requires CM_REFCNT register for sched timer for Integrator/CP board (integrator_defconfig). See http://infocenter.arm.com/help/topic/com.arm.doc.dui0138e/ch04s06s11.html Signed-off-by: Jan Petrous <jan.petrous@tieto.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10ACPI DSDT: Make control method `IQCR` serializedMichael S. Tsirkin4-6/+6
Forward-port the following commit from seabios: commit 995bbeef78b338370f426bf8d0399038c3fa259c Author: Paul Menzel <paulepanter@users.sourceforge.net> Date: Thu Oct 3 11:30:52 2013 +0200 The ASL Optimizing Compiler version 20130823-32 [Sep 11 2013] issues the following warning. $ make […] Compiling IASL out/src/fw/acpi-dsdt.hex out/src/fw/acpi-dsdt.dsl.i 360: Method(IQCR, 1, NotSerialized) { Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) […] ASL Input: out/src/fw/acpi-dsdt.dsl.i - 475 lines, 19181 bytes, 316 keywords AML Output: out/src/fw/acpi-dsdt.aml - 4407 bytes, 159 named objects, 157 executable opcodes Listing File: out/src/fw/acpi-dsdt.lst - 143715 bytes Hex Dump: out/src/fw/acpi-dsdt.hex - 41661 bytes Compilation complete. 0 Errors, 0 Warnings, 1 Remarks, 246 Optimizations […] After changing the parameter from `NotSerialized` to `Serialized`, the remark is indeed gone and there is no size change. The remark was added in ACPICA version 20130517 [1] and gives the following explanation. If a thread blocks within the method for any reason, and another thread enters the method, the method will fail because an attempt will be made to create the same (named) object twice. In this case, issue a remark that the method should be marked serialized. ACPICA BZ 909. [1] https://github.com/acpica/acpica/commit/ba84d0fc18ba910a47a3f71c68a43543c06e6831 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reported-by: Marcel Apfelbaum <marcel.a@redhat.com> Tested-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10acpi: strip compiler info in built-in DSDTMichael S. Tsirkin1-1/+7
IASL stores it's revision in each table header it generates. That's not nice since guests will see a change each time they move between hypervisors. We generally fill our own info for tables, but we (and seabios) forgot to do this for the built-in DSDT. Modifications in DSDT table: OEM ID: "BXPC" -> "BOCHS " OEM Table ID: "BXDSDT" -> "BXPCDSDT" Compiler ID: "INTL" -> "BXPC" Compiler Version: 0x20130823 -> 0x00000001 Tested-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10smbios: Set system manufacturer, product & version by defaultMarkus Armbruster3-1/+57
Currently, we get SeaBIOS defaults: manufacturer Bochs, product Bochs, no version. Best SeaBIOS can do, but we can provide better defaults: manufacturer QEMU, product & version taken from QEMUMachine desc and name. Take care to do this only for new machine types, of course. Note: Michael Tsirkin doesn't trust us to keep values of QEMUMachine member product stable in the future. Use copies instead, and in a way that makes it obvious that they're guest ABI. Note that we can be trusted to keep values of member name, because that has always been ABI. Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10spapr_pci: s/INT64_MAX/UINT64_MAX/Michael S. Tsirkin1-1/+1
It doesn't make sense for a region to be INT64_MAX in size: memory core uses UINT64_MAX as a special value meaning "all 64 bit" this is what was meant here. While this should never affect the spapr system which at the moment always has < 63 bit size, this makes us hit all kind of corner case bugs with sub-pages, so users are probably better off if we just use UINT64_MAX instead. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Alexander Graf <agraf@suse.de>
2013-12-10pc: s/INT64_MAX/UINT64_MAX/Paolo Bonzini2-2/+2
It doesn't make sense for a region to be INT64_MAX in size: memory core uses UINT64_MAX as a special value meaning "all 64 bit" this is what was meant here. While this should never affect the PC system which at the moment always has < 63 bit size, this makes us hit all kind of corner case bugs with sub-pages, so users are probably better off if we just use UINT64_MAX instead. Reported-by: Luiz Capitulino <lcapitulino@redhat.com> Tested-by: Luiz Capitulino <lcapitulino@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10pci: fix address space size for bridgeMichael S. Tsirkin1-1/+1
Address space size for bridge should be full 64 bit, so we should use UINT64_MAX not INT64_MAX as it's size. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10pc: map PCI address space as catchall region for not mapped addressesMichael S. Tsirkin4-60/+15
With a help of negative memory region priority PCI address space is mapped underneath RAM regions effectively catching every access to addresses not mapped by any other region. It simplifies PCI address space mapping into system address space. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com>
2013-12-09virtio: Convert exit to unrealizeAndreas Färber8-38/+49
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-12-09virtio: Complete converting VirtioDevice to QOM realizeAndreas Färber2-8/+1
Drop VirtioDeviceClass::init. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-12-09virtio-scsi: Convert to QOM realizeAndreas Färber2-33/+32
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-12-09virtio-rng: Convert to QOM realizeAndreas Färber1-13/+11
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-12-09virtio-balloon: Convert to QOM realizeAndreas Färber1-5/+6
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-12-09virtio-net: Convert to QOM realizeAndreas Färber1-4/+4
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-12-09virtio-serial: Convert to QOM realizeAndreas Färber1-8/+8
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-12-09virtio-blk: Convert to QOM realizeAndreas Färber1-12/+12
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-12-09virtio-9p: Convert to QOM realizeAndreas Färber1-21/+20
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-12-09virtio: Start converting VirtioDevice to QOM realizeAndreas Färber1-15/+27
Temporarily allow either VirtioDeviceClass::init or VirtioDeviceClass::realize. Introduce VirtioDeviceClass::unrealize for symmetry. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2025-03-06 08:21:38 +0000