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2018-02-12Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180212' ↵Peter Maydell8-69/+569
into staging ppc patch queue 2018-02-12 Here's the accumulatead ppc and pseries related patches for the last while. Highlights are: * A number of Macintosh / CUDA cleanups from Mark Cave-Ayland * An important bug fix (missing "break;") for H_GET_CPU_CHARACTERISTICS * Yet another fix for SMT mode handling * Assorted other cleanups and fixes # gpg: Signature made Mon 12 Feb 2018 03:39:30 GMT # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.12-20180212: misc: introduce new mos6522 VIA device and enable it for ppc builds cuda: factor out timebase-derived counter value and load time cuda: set timer 1 frequency property to CUDA_TIMER_FREQ cuda: don't call cuda_update() when writing to ACR register cuda: minor cosmetic tidy-ups to get_next_irq_time() cuda: rename frequency property to tb_frequency cuda: introduce CUDAState parameter to get_counter() spapr: set vsmt to MAX(8, smp_threads) cuda: don't allow writes to port output pins cuda: do not use old_mmio accesses hw/ppc: rename functions in comments spapr: add missing break in h_get_cpu_characteristics() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-11misc: introduce new mos6522 VIA device and enable it for ppc buildsMark Cave-Ayland3-0/+515
The MOS6522 VIA forms the bridge part of several Mac devices, including the Mac via-cuda and via-pmu devices. Introduce a standard mos6522 device that can be shared amongst multiple implementations. This is effectively taking the 6522 parts out of cuda.c and turning them into a separate device whilst also applying some style tidy-ups and including a conversion to trace-events. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-11cuda: factor out timebase-derived counter value and load timeMark Cave-Ayland1-9/+16
Commit b981289c49 "PPC: Cuda: Use cuda timer to expose tbfreq to guest" altered the timer calculations from those based upon the hardware CUDA clock frequency to those based upon the CPU timebase frequency. In fact we can isolate the differences to 2 simple changes: one to the counter read value and another to the counter load time. Move these changes into separate functions so the implementation can be swapped later. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-11cuda: set timer 1 frequency property to CUDA_TIMER_FREQMark Cave-Ayland1-5/+5
Now that we have successfully decoupled the timebase frequency and the hardware timer frequency, set the timer 1 frequency property to CUDA_TIMER_FREQ and alter get_next_irq_time() to use it rather than the hard-coded constant. In addition to this we must now switch the tb_diff calculation over to use the timebase frequency now that the hardware clock frequency and the timebase frequency are different. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> [dwg: Correct a conflict due to a bug in an earlier patch] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-11cuda: don't call cuda_update() when writing to ACR registerMark Cave-Ayland1-1/+0
The wire protocol for reading data to/from the VIA is triggered by changing inputs on port B rather than changing the timer configuration via the ACR. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-11cuda: minor cosmetic tidy-ups to get_next_irq_time()Mark Cave-Ayland1-11/+12
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-11cuda: rename frequency property to tb_frequencyMark Cave-Ayland3-5/+5
This allows us to more easily differentiate between the timebase frequency used to calibrate the MacOS timers and the actual frequency of the hardware clock as indicated by CUDA_TIMER_FREQ. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [dwg: Revert some extraneous changes which break compile] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-11cuda: introduce CUDAState parameter to get_counter()Mark Cave-Ayland1-5/+5
This will be required shortly and also happens to match nicely with the corresponding signature for set_counter(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-10spapr: set vsmt to MAX(8, smp_threads)Laurent Vivier1-1/+1
We ignore silently the value of smp_threads when we set the default VSMT value, and if smp_threads is greater than VSMT kernel is going into trouble later. Fixes: 8904e5a750 ("spapr: Adjust default VSMT value for better migration compatibility") Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-10cuda: don't allow writes to port output pinsMark Cave-Ayland1-2/+2
Use the direction registers as a mask to ensure that only input pins are updated upon write. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-10cuda: do not use old_mmio accessesMark Cave-Ayland1-32/+8
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-10machine: Polish -machine xxx,helpAlexey Kardashevskiy1-1/+1
The "-machine xxx,help" prints kernel-irqchip possible values as "OnOffSplit", this adds separators to the printed line. Also, since only lower case letters are specified in qapi/common.json, this changes the letter cases too. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2018-02-10hw/ppc: rename functions in commentsDaniel Henrique Barboza2-2/+3
Commit bcb5ce08cf ("spapr: Rename machine init functions for clarity") renamed ppc_spapr_reset to spapr_machine_reset and ppc_spapr_init to spapr_machine_init. Let's also rename the references in comments. Signed-off-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-10spapr: add missing break in h_get_cpu_characteristics()Greg Kurz1-0/+1
Detected by Coverity (CID 1385702). This fixes the recently added hypercall to let guests properly apply Spectre and Meltdown workarounds. Fixes: c59704b25473 "target/ppc/spapr: Add H-Call H_GET_CPU_CHARACTERISTICS" Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-09Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2018-02-07-v4' ↵Peter Maydell88-63/+74
into staging Miscellaneous patches for 2018-02-07 # gpg: Signature made Fri 09 Feb 2018 12:52:51 GMT # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-misc-2018-02-07-v4: Move include qemu/option.h from qemu-common.h to actual users Drop superfluous includes of qapi/qmp/qjson.h Drop superfluous includes of qapi/qmp/dispatch.h Include qapi/qmp/qnull.h exactly where needed Include qapi/qmp/qnum.h exactly where needed Include qapi/qmp/qbool.h exactly where needed Include qapi/qmp/qstring.h exactly where needed Include qapi/qmp/qdict.h exactly where needed Include qapi/qmp/qlist.h exactly where needed Include qapi/qmp/qobject.h exactly where needed qdict qlist: Make most helper macros functions Eliminate qapi/qmp/types.h Typedef the subtypes of QObject in qemu/typedefs.h, too Include qmp-commands.h exactly where needed Drop superfluous includes of qapi/qmp/qerror.h Include qapi/error.h exactly where needed Drop superfluous includes of qapi-types.h and test-qapi-types.h Clean up includes Use #include "..." for our own headers, <...> for others vnc: use stubs for CONFIG_VNC=n dummy functions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-09Merge remote-tracking branch ↵Peter Maydell19-76/+1320
'remotes/pmaydell/tags/pull-target-arm-20180209' into staging target-arm queue: * Support M profile derived exceptions on exception entry and exit * Implement AArch64 v8.2 crypto insns (SHA-512, SHA-3, SM3, SM4) * Implement working i.MX6 SD controller * Various devices preparatory to i.MX7 support * Preparatory patches for SVE emulation * v8M: Fix bug in implementation of 'TT' insn * Give useful error if user tries to use userspace GICv3 with KVM # gpg: Signature made Fri 09 Feb 2018 11:01:23 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180209: (30 commits) hw/core/generic-loader: Allow PC to be set on command line target/arm/translate.c: Fix missing 'break' for TT insns target/arm/kvm: gic: Prevent creating userspace GICv3 with KVM target/arm: Add SVE state to TB->FLAGS target/arm: Add ZCR_ELx target/arm: Add SVE to migration state target/arm: Add predicate registers for SVE target/arm: Expand vector registers for SVE hw/arm: Move virt's PSCI DT fixup code to arm/boot.c usb: Add basic code to emulate Chipidea USB IP i.MX: Add implementation of i.MX7 GPR IP block i.MX: Add i.MX7 GPT variant i.MX: Add code to emulate GPCv2 IP block i.MX: Add code to emulate i.MX7 SNVS IP-block i.MX: Add code to emulate i.MX2 watchdog IP block i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks hw: i.MX: Convert i.MX6 to use TYPE_IMX_USDHC sdhci: Add i.MX specific subtype of SDHCI target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support target/arm: implement SM4 instructions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-09Move include qemu/option.h from qemu-common.h to actual usersMarkus Armbruster20-5/+21
qemu-common.h includes qemu/option.h, but most places that include the former don't actually need the latter. Drop the include, and add it to the places that actually need it. While there, drop superfluous includes of both headers, and separate #include from file comment with a blank line. This cleanup makes the number of objects depending on qemu/option.h drop from 4545 (out of 4743) to 284 in my "build everything" tree. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-20-armbru@redhat.com> [Semantic conflict with commit bdd6a90a9e in block/nvme.c resolved]
2018-02-09Drop superfluous includes of qapi/qmp/qjson.hMarkus Armbruster3-3/+0
Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-19-armbru@redhat.com>
2018-02-09Include qapi/qmp/qbool.h exactly where neededMarkus Armbruster1-1/+0
Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-15-armbru@redhat.com>
2018-02-09Include qapi/qmp/qdict.h exactly where neededMarkus Armbruster4-0/+4
This cleanup makes the number of objects depending on qapi/qmp/qdict.h drop from 4550 (out of 4743) to 368 in my "build everything" tree. For qapi/qmp/qobject.h, the number drops from 4552 to 390. While there, separate #include from file comment with a blank line. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-13-armbru@redhat.com>
2018-02-09qdict qlist: Make most helper macros functionsMarkus Armbruster2-0/+2
The macro expansions of qdict_put_TYPE() and qlist_append_TYPE() need qbool.h, qnull.h, qnum.h and qstring.h to compile. We include qnull.h and qnum.h in the headers, but not qbool.h and qstring.h. Works, because we include those wherever the macros get used. Open-coding these helpers is of dubious value. Turn them into functions and drop the includes from the headers. This cleanup makes the number of objects depending on qapi/qmp/qnum.h from 4551 (out of 4743) to 46 in my "build everything" tree. For qapi/qmp/qnull.h, the number drops from 4552 to 21. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-10-armbru@redhat.com>
2018-02-09Eliminate qapi/qmp/types.hMarkus Armbruster2-2/+0
qapi/qmp/types.h is a convenience header to include a number of qapi/qmp/ headers. Since we rarely need all of the headers qapi/qmp/types.h includes, we bypass it most of the time. Most of the places that use it don't need all the headers, either. Include the necessary headers directly, and drop qapi/qmp/types.h. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-9-armbru@redhat.com>
2018-02-09Include qmp-commands.h exactly where neededMarkus Armbruster5-5/+0
Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-7-armbru@redhat.com> [OSX breakage fixed]
2018-02-09Drop superfluous includes of qapi/qmp/qerror.hMarkus Armbruster1-1/+0
Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-6-armbru@redhat.com>
2018-02-09Include qapi/error.h exactly where neededMarkus Armbruster59-30/+42
This cleanup makes the number of objects depending on qapi/error.h drop from 1910 (out of 4743) to 1612 in my "build everything" tree. While there, separate #include from file comment with a blank line, and drop a useless comment on why qemu/osdep.h is included first. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-5-armbru@redhat.com> [Semantic conflict with commit 34e304e975 resolved, OSX breakage fixed]
2018-02-09hw/core/generic-loader: Allow PC to be set on command linePeter Maydell1-1/+1
The documentation for the generic loader claims that you can set the PC for a CPU with an option of the form -device loader,cpu-num=0,addr=0x10000004 However if you try this QEMU complains: cpu_num must be specified when setting a program counter This is because we were testing against 0 rather than CPU_NONE. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180205150426.20542-1-peter.maydell@linaro.org
2018-02-09hw/arm: Move virt's PSCI DT fixup code to arm/boot.cAndrey Smirnov2-61/+65
Move virt's PSCI DT fixup code to arm/boot.c and set this fixup to happen automatically for every board that doesn't mark "psci-conduit" as disabled. This way emulated boards other than "virt" that rely on PSIC for SMP could benefit from that code. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-09usb: Add basic code to emulate Chipidea USB IPAndrey Smirnov2-0/+177
Add code to emulate Chipidea USB IP (used in i.MX SoCs). Tested to work against: -usb -drive if=none,id=stick,file=usb.img,format=raw -device \ usb-storage,bus=usb-bus.0,drive=stick Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-09i.MX: Add implementation of i.MX7 GPR IP blockAndrey Smirnov3-0/+129
Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-09i.MX: Add i.MX7 GPT variantAndrey Smirnov1-0/+25
Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-09i.MX: Add code to emulate GPCv2 IP blockAndrey Smirnov2-1/+126
Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-09i.MX: Add code to emulate i.MX7 SNVS IP-blockAndrey Smirnov2-0/+84
Add code to emulate SNVS IP-block. Currently only the bits needed to be able to emulate machine shutdown are implemented. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-09i.MX: Add code to emulate i.MX2 watchdog IP blockAndrey Smirnov2-0/+90
Add enough code to emulate i.MX2 watchdog IP block so it would be possible to reboot the machine running Linux Guest. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-09i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocksAndrey Smirnov2-0/+278
Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-09hw: i.MX: Convert i.MX6 to use TYPE_IMX_USDHCAndrey Smirnov1-1/+1
Convert i.MX6 to use TYPE_IMX_USDHC since that's what real HW comes with. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-09sdhci: Add i.MX specific subtype of SDHCIAndrey Smirnov2-1/+252
IP block found on several generations of i.MX family does not use vanilla SDHCI implementation and it comes with a number of quirks. Introduce i.MX SDHCI subtype of SDHCI block to add code necessary to support unmodified Linux guest driver. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMM: define and use ESDHC_UNDOCUMENTED_REG27] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-09target/arm: Split "get pending exception info" from "acknowledge it"Peter Maydell2-8/+25
Currently armv7m_nvic_acknowledge_irq() does three things: * make the current highest priority pending interrupt active * return a bool indicating whether that interrupt is targeting Secure or NonSecure state * implicitly tell the caller which is the highest priority pending interrupt by setting env->v7m.exception We need to split these jobs, because v7m_exception_taken() needs to know whether the pending interrupt targets Secure so it can choose to stack callee-saves registers or not, but it must not make the interrupt active until after it has done that stacking, in case the stacking causes a derived exception. Similarly, it needs to know the number of the pending interrupt so it can read the correct vector table entry before the interrupt is made active, because vector table reads might also cause a derived exception. Create a new armv7m_nvic_get_pending_irq_info() function which simply returns information about the highest priority pending interrupt, and use it to rearrange the v7m_exception_taken() code so we don't acknowledge the exception until we've done all the things which could possibly cause a derived exception. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1517324542-6607-3-git-send-email-peter.maydell@linaro.org
2018-02-09target/arm: Add armv7m_nvic_set_pending_derived()Peter Maydell2-3/+67
In order to support derived exceptions (exceptions generated in the course of trying to take an exception), we need to be able to handle prioritizing whether to take the original exception or the derived exception. We do this by introducing a new function armv7m_nvic_set_pending_derived() which the exception-taking code in helper.c will call when a derived exception occurs. Derived exceptions are dealt with mostly like normal pending exceptions, so we share the implementation with the armv7m_nvic_set_pending() function. Note that the way we structure this is significantly different from the v8M Arm ARM pseudocode: that does all the prioritization logic in the DerivedLateArrival() function, whereas we choose to let the existing "identify highest priority exception" logic do the prioritization for us. The effect is the same, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1517324542-6607-2-git-send-email-peter.maydell@linaro.org
2018-02-09s390x/pci: use the right pal and pba in reg_ioat()Yi Min Zhao1-0/+2
When registering ioat, pba should be comprised of leftmost 52 bits and rightmost 12 binary zeros, and pal should be comprised of leftmost 52 bits and right most 12 binary ones. The lower 12 bits of words 5 and 7 of the FIB are ignored by the facility. Let's fixup this. Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Message-Id: <20180205072258.5968-4-zyimin@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/pci: fixup global refreshYi Min Zhao3-15/+63
The VFIO common code doesn't provide the possibility to modify a previous mapping entry in another way than unmapping and mapping again with new properties. To avoid -EEXIST DMA mapping error, we introduce a GHashTable to store S390IOTLBEntry instances in order to cache the mapped entries. When intercepting rpcit instruction, ignore the identical mapped entries to avoid doing map operations multiple times and do unmap and re-map operations for the case of updating the valid entries. Acked-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Message-Id: <20180205072258.5968-3-zyimin@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/pci: fixup the code walking IOMMU tablesYi Min Zhao3-78/+225
Current s390x PCI IOMMU code is lack of flags' checking, including: 1) protection bit 2) table length 3) table offset 4) intermediate tables' invalid bit 5) format control bit This patch introduces a new struct named S390IOTLBEntry, and makes up these missed checkings. At the same time, inform the guest with the corresponding error number when the check fails. Finally, in order to get the error number, we export s390_guest_io_table_walk(). Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Message-Id: <20180205072258.5968-2-zyimin@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/sclp: fix event mask handlingChristian Borntraeger1-2/+2
commit 67915de9f038 ("s390x/event-facility: variable-length event masks") switched the sclp receive/send mask. This broke the sclp lm console. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Fixes: commit 67915de9f038 ("s390x/event-facility: variable-length event masks") Cc: Cornelia Huck <cohuck@redhat.com> Cc: Jason J. Herne <jjherne@linux.vnet.ibm.com> Cc: qemu-stable@nongnu.org Message-Id: <20180202094241.59537-1-borntraeger@de.ibm.com> Reviewed-by: Claudio Imbrenda <imbrenda@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: cache the common flic class in a central functionDavid Hildenbrand3-8/+19
This avoids tons of conversions when handling interrupts. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-19-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/kvm: cache the kvm flic in a central functionDavid Hildenbrand1-5/+16
This avoids tons of conversions when handling interrupts. Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-18-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: cache the qemu flic in a central functionDavid Hildenbrand1-6/+17
This avoids tons of conversions when handling interrupts. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: remove SMP warningDavid Hildenbrand1-4/+0
We should be pretty good in shape now. Floating interrupts are working and atomic instructions should be atomic. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: optimize CPU wakeup for TCGDavid Hildenbrand1-2/+29
Kicking all CPUs on every floating interrupt is far from efficient. Let's optimize it at least a little bit. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: implement qemu_s390_clear_io_flic()David Hildenbrand1-2/+29
Now that we have access to the io interrupts, we can implement clear_io_irq() for TCG. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: make floating interrupts on TCG actually floatingDavid Hildenbrand1-10/+134
Move floating interrupt handling into the flic. Floating interrupts will now be considered by all CPUs, not just CPU #0. While at it, convert I/O interrupts to use a list and make sure we properly consider I/O sub-classes in s390_cpu_has_io_int(). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: no need to call s390_io_interrupt() from flicDavid Hildenbrand1-1/+2
We can directly call the right function. Suggested-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
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