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2022-07-15hw/nvme: force nvme-ns param 'shared' to false if no nvme-subsys nodeNiklas Cassel1-0/+2
Since commit 916b0f0b5264 ("hw/nvme: change nvme-ns 'shared' default") the default value of nvme-ns param 'shared' is set to true, regardless if there is a nvme-subsys node or not. On a system without a nvme-subsys node, a namespace will never be able to be attached to more than one controller, so for this configuration, it is counterintuitive for this parameter to be set by default. Force the nvme-ns param 'shared' to false for configurations where there is no nvme-subsys node, as the namespace will never be able to attach to more than one controller anyway. Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-07-15hw/nvme: Add trace events for shadow doorbell bufferJinhao Fan2-0/+10
When shadow doorbell buffer is enabled, doorbell registers are lazily updated. The actual queue head and tail pointers are stored in Shadow Doorbell buffers. Add trace events for updates on the Shadow Doorbell buffers and EventIdx buffers. Also add trace event for the Doorbell Buffer Config command. Signed-off-by: Jinhao Fan <fanjinhao21s@ict.ac.cn> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Keith Busch <kbusch@kernel.org> [k.jensen: rebased] Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-07-15hw/nvme: Implement shadow doorbell buffer supportJinhao Fan2-1/+122
Implement Doorbel Buffer Config command (Section 5.7 in NVMe Spec 1.3) and Shadow Doorbel buffer & EventIdx buffer handling logic (Section 7.13 in NVMe Spec 1.3). For queues created before the Doorbell Buffer Config command, the nvme_dbbuf_config function tries to associate each existing SQ and CQ with its Shadow Doorbel buffer and EventIdx buffer address. Queues created after the Doorbell Buffer Config command will have the doorbell buffers associated with them when they are initialized. In nvme_process_sq and nvme_post_cqe, proactively check for Shadow Doorbell buffer changes instead of wait for doorbell register changes. This reduces the number of MMIOs. In nvme_process_db(), update the shadow doorbell buffer value with the doorbell register value if it is the admin queue. This is a hack since hosts like Linux NVMe driver and SPDK do not use shadow doorbell buffer for the admin queue. Copying the doorbell register value to the shadow doorbell buffer allows us to support these hosts as well as spec-compliant hosts that use shadow doorbell buffer for the admin queue. Signed-off-by: Jinhao Fan <fanjinhao21s@ict.ac.cn> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Keith Busch <kbusch@kernel.org> [k.jensen: rebased] Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-07-12Merge tag 'pull-block-2022-07-12' of https://gitlab.com/hreitz/qemu into stagingPeter Maydell19-91/+92
Block patches: - Refactoring for non-coroutine variants of bdrv/blk_co_* functions: Auto-generate more of them with the block coroutine wrapper generator script - iotest fixes - Both for the storage daemon and the system emulator: Fix PID file handling when daemonizing (store the absolute path and delete that on exit, which is necessary because daemonizing will change the working directory to /) # gpg: Signature made Tue 12 Jul 2022 19:04:14 BST # gpg: using RSA key CB62D7A0EE3829E45F004D34A1FA40D098019CDF # gpg: issuer "hreitz@redhat.com" # gpg: Good signature from "Hanna Reitz <hreitz@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: CB62 D7A0 EE38 29E4 5F00 4D34 A1FA 40D0 9801 9CDF * tag 'pull-block-2022-07-12' of https://gitlab.com/hreitz/qemu: (35 commits) vl: Unlink absolute PID file path vl: Conditionally register PID file unlink notifier qsd: Unlink absolute PID file path iotests/297: Have mypy ignore unused ignores qsd: Do not use error_report() before monitor_init block: Remove remaining unused symbols in coroutines.h block: Reorganize some declarations in block-backend-io.h block: Add blk_co_truncate() block: Add blk_co_ioctl() block: Implement blk_flush() using generated_co_wrapper block: Implement blk_pdiscard() using generated_co_wrapper block: Implement blk_pwrite_zeroes() using generated_co_wrapper block: Add blk_co_pwrite_compressed() block: Change blk_pwrite_compressed() param order block: Export blk_pwritev_part() in block-backend-io.h block: Add blk_[co_]preadv_part() block: Add blk_{preadv,pwritev}() block: Implement blk_{pread,pwrite}() using generated_co_wrapper block: Make blk_co_pwrite() take a const buffer block: Make 'bytes' param of blk_{pread,pwrite}() an int64_t ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-12Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell1-1/+2
* fuzzing fixes (Alexander) * fix cross compilation CFLAGS and compiler choice * do not specify -bios option for tests/vm * miscellaneous fixes * preparation for pre-install tree in the build directory (Akihiko) # gpg: Signature made Tue 12 Jul 2022 13:47:19 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: meson: place default firmware path under .../share qga: Relocate a path emitted in the help text build: Do not depend on pc-bios for config-host.mak accel: kvm: Fix memory leak in find_stats_descriptors audio/dbus: fix building fuzz: only use generic-fuzz targets on oss-fuzz build: improve -fsanitize-coverage-allowlist check build: try both native and cross compilers configure: pass whole target name to probe_target_compiler tests/tcg: compile system emulation tests as freestanding configure: write EXTRA_CFLAGS for all sub-Makefiles configure: allow more host/target combos to use the host compiler configure, pc-bios/vof: pass cross CFLAGS correctly configure, pc-bios/s390-ccw: pass cross CFLAGS correctly configure, pc-bios/optionrom: pass cross CFLAGS correctly pc-bios/optionrom: use -m16 unconditionally scsi/lsi53c895a: fix use-after-free in lsi_do_msgout (CVE-2022-0216) tests/vm: do not specify -bios option Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # pc-bios/s390-ccw/netboot.mak
2022-07-12block: Change blk_{pread,pwrite}() param orderAlberto Faria19-83/+84
Swap 'buf' and 'bytes' around for consistency with blk_co_{pread,pwrite}(), and in preparation to implement these functions using generated_co_wrapper. Callers were updated using this Coccinelle script: @@ expression blk, offset, buf, bytes, flags; @@ - blk_pread(blk, offset, buf, bytes, flags) + blk_pread(blk, offset, bytes, buf, flags) @@ expression blk, offset, buf, bytes, flags; @@ - blk_pwrite(blk, offset, buf, bytes, flags) + blk_pwrite(blk, offset, bytes, buf, flags) It had no effect on hw/block/nand.c, presumably due to the #if, so that file was updated manually. Overly-long lines were then fixed by hand. Signed-off-by: Alberto Faria <afaria@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220705161527.1054072-4-afaria@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2022-07-12block: Add a 'flags' param to blk_pread()Alberto Faria17-31/+31
For consistency with other I/O functions, and in preparation to implement it using generated_co_wrapper. Callers were updated using this Coccinelle script: @@ expression blk, offset, buf, bytes; @@ - blk_pread(blk, offset, buf, bytes) + blk_pread(blk, offset, buf, bytes, 0) It had no effect on hw/block/nand.c, presumably due to the #if, so that file was updated manually. Overly-long lines were then fixed by hand. Signed-off-by: Alberto Faria <afaria@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220705161527.1054072-3-afaria@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2022-07-12block: Make blk_{pread,pwrite}() return 0 on successAlberto Faria6-16/+16
They currently return the value of their 'bytes' parameter on success. Make them return 0 instead, for consistency with other I/O functions and in preparation to implement them using generated_co_wrapper. This also makes it clear that short reads/writes are not possible. Signed-off-by: Alberto Faria <afaria@redhat.com> Message-Id: <20220705161527.1054072-2-afaria@redhat.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2022-07-07hw/arm/virt: dt: add rng-seed propertyJason A. Donenfeld1-17/+27
In 60592cfed2 ("hw/arm/virt: dt: add kaslr-seed property"), the kaslr-seed property was added, but the equally as important rng-seed property was forgotten about, which has identical semantics for a similar purpose. This commit implements it in exactly the same way as kaslr-seed. It then changes the name of the disabling option to reflect that this has more to do with randomness vs determinism, rather than something particular about kaslr. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> [PMM: added deprecated.rst section for the deprecation] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-07Merge tag 'pull-ppc-20220706' of https://gitlab.com/danielhb/qemu into stagingRichard Henderson13-162/+374
ppc patch queue for 2022-07-06: This queue consists of improvements and bug fixes in TCG, powernv and pSeries, with some fixes in other areas as well. - tcg and target/ppc: BCDA and mffscdrn implementations, Remove CONFIG_INT128 conditional code - fix '-cpu max' alias - remove '-cpu default' alias - spapr: fixes in DDW handling, H_WATCHDOG support - powernv: cleanups in the pnv-phb3/4 models - fix core type of MPC8555 and MPC8560 models # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCYsXrpgAKCRA82cqW3gMx # ZBe9AP4oqMTFw7r9EQPJU4QFMUeAVABl4o0xNb2wLyYov9CtKAD+LoVERSmtLTJ1 # kFpgBrRTWKVylaLEdZQoTdFlJeBwzQg= # =GPG1 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 07 Jul 2022 01:38:06 AM +0530 # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20220706' of https://gitlab.com/danielhb/qemu: (34 commits) target/ppc: Fix MPC8555 and MPC8560 core type to e500v1 target/ppc/cpu-models: Remove the "default" CPU alias target/ppc: Return default CPU for max CPU target/ppc: implement cdtbcd target/ppc: implement cbcdtd target/ppc: implement addg6s target/ppc: Add flag for ISA v2.06 BCDA instructions tests/tcg/ppc64: Add mffsce test target/ppc: Implement mffscdrn[i] instructions target/ppc: Move mffs[.] to decodetree target/ppc: Move mffsl to decodetree target/ppc: Move mffsce to decodetree target/ppc: Move mffscrn[i] to decodetree target/ppc: Fix insn32.decode style issues ppc/spapr: Implement H_WATCHDOG ppc: Define SETFIELD for the ppc target target/ppc: use int128.h methods in vsubcuq target/ppc: use int128.h methods in vsubecuq and vsubeuqm target/ppc: use int128.h methods in vsubuqm target/ppc: use int128.h methods in vaddcuq ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-06ppc/spapr: Implement H_WATCHDOGAlexey Kardashevskiy4-0/+286
The new PAPR 2.12 defines a watchdog facility managed via the new H_WATCHDOG hypercall. This adds H_WATCHDOG support which a proposed driver for pseries uses: https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=303120 This was tested by running QEMU with a debug kernel and command line: -append \ "pseries-wdt.timeout=60 pseries-wdt.nowayout=1 pseries-wdt.action=2" and running "echo V > /dev/watchdog0" inside the VM. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220622051008.1067464-1-aik@ozlabs.ru> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-07-06ppc: Define SETFIELD for the ppc targetAlexey Kardashevskiy3-56/+0
It keeps repeating, move it to the header. This uses __builtin_ffsll() to allow using the macros in #define. This is not using the QEMU's FIELD macros as this would require changing all such macros found in skiboot (the PPC PowerNV firmware). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220628080544.1509428-1-aik@ozlabs.ru> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-07-06spapr/ddw: Implement 64bit query extensionAlexey Kardashevskiy2-6/+18
PAPR 2.8 (2018) defines an extension to return 64bit value for the largest TCE block in "ibm,query-pe-dma-window". Recent Linux kernels support this already. This adds the extension and supports the older format. This advertises a bigger window for the new format as the biggest window with 2M pages below the start of the 64bit window as it is the maximum we will see in practice. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220623073136.1380214-1-aik@ozlabs.ru> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-07-06spapr/ddw: Reset DMA when the last non-default window is removedAlexey Kardashevskiy3-1/+18
PAPR+/LoPAPR says: === The platform must restore the default DMA window for the PE on a call to the ibm,remove-pe-dma-window RTAS call when all of the following are true: a. The call removes the last DMA window remaining for the PE. b. The DMA window being removed is not the default window === This resets DMA as PAPR mandates. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220622052955.1069903-1-aik@ozlabs.ru> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-07-06ppc/pnv: remove 'INTERFACE_PCIE_DEVICE' from phb4 root busDaniel Henrique Barboza1-4/+0
It's unneeded. No other PCIE_BUS implements this interface. Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Fixes: 4f9924c4d4cf ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge") Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220621173436.165912-9-danielhb413@gmail.com>
2022-07-06ppc/pnv: remove 'INTERFACE_PCIE_DEVICE' from phb3 root busDaniel Henrique Barboza1-4/+0
It's unneeded. No other PCIE_BUS implements this interface. Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Fixes: 9ae1329ee2fe ("ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridge") Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220621173436.165912-8-danielhb413@gmail.com>
2022-07-06ppc/pnv: make pnv_chip_power8_pic_print_info() use chip8->phbs[]Daniel Henrique Barboza1-14/+8
It's inneficient to scroll all child objects when we have all PHBs available in chip8->phbs[]. pnv_chip_power8_pic_print_info_child() ended up folded into pic_print_info() for simplicity. Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220621173436.165912-7-danielhb413@gmail.com>
2022-07-06ppc/pnv: make pnv_ics_resend() use chip8->phbs[]Daniel Henrique Barboza1-14/+8
pnv_ics_resend() is scrolling through all the child objects of the chip to search for the PHBs. It's faster and simpler to just use the phbs[] array. pnv_ics_resend_child() was folded into pnv_ics_resend() since it's too simple to justify its own function. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220621173436.165912-6-danielhb413@gmail.com>
2022-07-06ppc/pnv: make pnv_ics_get() use the chip8->phbs[] arrayDaniel Henrique Barboza1-27/+11
The function is working today by getting all the child objects of the chip, interacting with each of them to check whether the child is a PHB, and then doing what needs to be done. We have all the chip PHBs in the phbs[] array so interacting with all child objects is unneeded. Open code pnv_ics_get_phb_ics() into pnv_ics_get() and remove both pnv_ics_get_phb_ics() and the ForeachPhb3Args struct. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220621173436.165912-5-danielhb413@gmail.com>
2022-07-06ppc/pnv: assign pnv-phb-root-port chassis/slot earlierDaniel Henrique Barboza3-34/+17
It is not advisable to execute an object_dynamic_cast() to poke into bus->qbus.parent and follow it up with a C cast into the PnvPHB type we think we got. In fact this is not needed. There is nothing sophisticated being done with the PHB object retrieved during root_port_realize() for both PHB3 and PHB4. We're retrieving a PHB reference just to access phb->chip_id and phb->phb_id and use them to define the chassis/slot of the root port. phb->phb_id is already being passed to pnv_phb_attach_root_port() via the 'index' parameter. Let's also add a 'chip_id' parameter to this function and assign chassis and slot right there. This will spare us from the hassle of accessing the PHB object inside realize(). Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220621173436.165912-4-danielhb413@gmail.com>
2022-07-06ppc/pnv: attach phb3/phb4 root ports in QOM treeDaniel Henrique Barboza3-3/+8
At this moment we leave the pnv-phb3(4)-root-port unattached in QOM: /unattached (container) (...) /device[2] (pnv-phb3-root-port) /bus master container[0] (memory-region) /bus master[0] (memory-region) /pci_bridge_io[0] (memory-region) /pci_bridge_io[1] (memory-region) /pci_bridge_mem[0] (memory-region) /pci_bridge_pci[0] (memory-region) /pci_bridge_pref_mem[0] (memory-region) /pci_bridge_vga_io_hi[0] (memory-region) /pci_bridge_vga_io_lo[0] (memory-region) /pci_bridge_vga_mem[0] (memory-region) /pcie.0 (PCIE) Let's make changes in pnv_phb_attach_root_port() to attach the created root ports to its corresponding PHB. This is the result afterwards: /pnv-phb3[0] (pnv-phb3) /lsi (ics) /msi (phb3-msi) /msi32[0] (memory-region) /msi64[0] (memory-region) /pbcq (pnv-pbcq) (...) /phb3_iommu[0] (pnv-phb3-iommu-memory-region) /pnv-phb3-root.0 (pnv-phb3-root) /pnv-phb3-root-port[0] (pnv-phb3-root-port) /bus master container[0] (memory-region) /bus master[0] (memory-region) /pci_bridge_io[0] (memory-region) /pci_bridge_io[1] (memory-region) /pci_bridge_mem[0] (memory-region) /pci_bridge_pci[0] (memory-region) /pci_bridge_pref_mem[0] (memory-region) /pci_bridge_vga_io_hi[0] (memory-region) /pci_bridge_vga_io_lo[0] (memory-region) /pci_bridge_vga_mem[0] (memory-region) /pcie.0 (PCIE) Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220621173436.165912-3-danielhb413@gmail.com>
2022-07-06ppc/pnv: move root port attach to pnv_phb4_realize()Daniel Henrique Barboza2-3/+4
Creating a root port is something related to the PHB, not the PEC. It also makes the logic more in line with what pnv-phb3 does. Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220621173436.165912-2-danielhb413@gmail.com>
2022-07-06m68k: virt: pass RNG seed via bootinfo blockJason A. Donenfeld2-0/+23
This commit wires up bootinfo's RNG seed attribute so that Linux VMs can have their RNG seeded from the earliest possible time in boot, just like the "rng-seed" device tree property on those platforms. The link contains the corresponding Linux patch. Link: https://lore.kernel.org/lkml/20220626111509.330159-1-Jason@zx2c4.com/ Based-on: <20220625152318.120849-1-Jason@zx2c4.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Message-Id: <20220626111804.330745-1-Jason@zx2c4.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-07-06m68k: use correct variable name in boot info string macroJason A. Donenfeld1-1/+1
Every time this macro is used, the caller is passing in "parameters_base", so this bug wasn't spotted. But the actual macro variable name is "base", so use that instead. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220625152318.120849-1-Jason@zx2c4.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-07-06scsi/lsi53c895a: fix use-after-free in lsi_do_msgout (CVE-2022-0216)Mauro Matteo Cascella1-1/+2
Set current_req->req to NULL to prevent reusing a free'd buffer in case of repeated SCSI cancel requests. Thanks to Thomas Huth for suggesting the patch. Fixes: CVE-2022-0216 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/972 Signed-off-by: Mauro Matteo Cascella <mcascell@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220705200543.2366809-1-mcascell@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-07-06e1000: set RX descriptor status in a separate operationDing Hui1-1/+4
The code of setting RX descriptor status field maybe work fine in previously, however with the update of glibc version, it shows two issues when guest using dpdk receive packets: 1. The dpdk has a certain probability getting wrong buffer_addr this impact may be not obvious, such as lost a packet once in a while 2. The dpdk may consume a packet twice when scan the RX desc queue over again this impact will lead a infinite wait in Qemu, since the RDT (tail pointer) be inscreased to equal to RDH by unexpected, which regard as the RX desc queue is full Write a whole of RX desc with DD flag on is not quite correct, because when the underlying implementation of memcpy using XMM registers to copy e1000_rx_desc (when AVX or something else CPU feature is usable), the bytes order of desc writing to memory is indeterminacy We can use full-scale test case to reproduce the issue-2 by https://github.com/BASM/qemu_dpdk_e1000_test (thanks to Leonid Myravjev) I also write a POC test case at https://github.com/cdkey/e1000_poc which can reproduce both of them, and easy to verify the patch effect. The hw watchpoint also shows that, when Qemu using XMM related instructions writing 16 bytes e1000_rx_desc, concurrent with DPDK using movb writing 1 byte status, the final result of writing to memory will be one of them, if it made by Qemu which DD flag is on, DPDK will consume it again. Setting DD status in a separate operation, can prevent the impact of disorder memory writing by memcpy, also avoid unexpected data when concurrent writing status by qemu and guest dpdk. Links: https://lore.kernel.org/qemu-devel/20200102110504.GG121208@stefanha-x1.localdomain/T/ Reported-by: Leonid Myravjev <asm@asm.pp.ru> Cc: Stefan Hajnoczi <stefanha@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-stable@nongnu.org Tested-by: Jing Zhang <zhangjing@sangfor.com.cn> Reviewed-by: Frank Lee <lifan38153@sangfor.com.cn> Signed-off-by: Ding Hui <dinghui@sangfor.com.cn> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-07-05xen/pass-through: don't create needless register groupChuck Zmudzinski1-5/+9
Currently we are creating a register group for the Intel IGD OpRegion for every device we pass through, but the XEN_PCI_INTEL_OPREGION register group is only valid for an Intel IGD. Add a check to make sure the device is an Intel IGD and a check that the administrator has enabled gfx_passthru in the xl domain configuration. Require both checks to be true before creating the register group. Use the existing is_igd_vga_passthrough() function to check for a graphics device from any vendor and that the administrator enabled gfx_passthru in the xl domain configuration, but further require that the vendor be Intel, because only Intel IGD devices have an Intel OpRegion. These are the same checks hvmloader and libxl do to determine if the Intel OpRegion needs to be mapped into the guest's memory. Also, move the comment about trapping 0xfc for the Intel OpRegion where it belongs after applying this patch. Signed-off-by: Chuck Zmudzinski <brchuckz@aol.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <c76dff6369ccf2256bd9eed5141da1db767293d2.1656480662.git.brchuckz@aol.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2022-07-05xen/pass-through: merge emulated bits correctlyChuck Zmudzinski1-5/+6
In xen_pt_config_reg_init(), there is an error in the merging of the emulated data with the host value. With the current Qemu, instead of merging the emulated bits with the host bits as defined by emu_mask, the emulated bits are merged with the host bits as defined by the inverse of emu_mask. In some cases, depending on the data in the registers on the host, the way the registers are setup, and the initial values of the emulated bits, the end result will be that the register is initialized with the wrong value. To correct this error, use the XEN_PT_MERGE_VALUE macro to help ensure the merge is done correctly. This correction is needed to resolve Qemu project issue #1061, which describes the failure of Xen HVM Linux guests to boot in certain configurations with passed through PCI devices, that is, when this error disables instead of enables the PCI_STATUS_CAP_LIST bit of the PCI_STATUS register of a passed through PCI device, which in turn disables the MSI-X capability of the device in Linux guests with the end result being that the Linux guest never completes the boot process. Fixes: 2e87512eccf3 ("xen/pt: Sync up the dev.config and data values") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1061 Buglink: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=988333 Signed-off-by: Chuck Zmudzinski <brchuckz@aol.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <e4392535d8e5266063dc5461d0f1d301e3dd5951.1656522217.git.brchuckz@aol.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2022-07-05hw/intc/loongarch_ipi: Fix mail send and any send functionXiaojuan Yang1-23/+31
By the document of ipi mailsend device, byte is written only when the mask bit is 0. The original code discards mask bit and overwrite the data always, this patch fixes the issue. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Message-Id: <20220705064901.2353349-3-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-05hw/intc/loongarch_ipi: Fix ipi device access of 64bitsXiaojuan Yang2-8/+35
In general loongarch ipi device, 32bit registers is emulated, however for anysend/mailsend device only 64bit register access is supported. So separate the ipi memory region into two regions, including 32 bits and 64 bits. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Message-Id: <20220705064901.2353349-2-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-05hw/rtc/ls7a_rtc: Drop unused inline functionsRichard Henderson1-21/+6
Remove toy_val_to_time_mon and toy_val_to_time_year as unused, to avoid a build failure with clang. Remove all of the other inline markers too so that this does not creep back in. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04Merge tag 'pull-la-20220704' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson3-80/+74
LoongArch patch queue: Support linux-user. Fixes for CSR BADV. Fix ASRT{LE,GT} exception. Fixes for LS7A RTC. Fix for interrupt vector spacing. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmLCs4gdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV89IQgAsgGM117dgDlI48wP # zRVRE9rmK9EE/YR8b4rejh5iFlH0kZTELWAaXmjxWSv9uyXwsApNdnxnthUH1CRD # RbT8AOIUphH6MBMb2joy+zFyBkGBnJQbSxJWN0jDT/ie67I/O0qOIemXU9tETssn # OLNCn+GuNFLiS8EytczkZHDmQjjt00PGZLsnCm+ZY+/ejNci0FV0NItBo6iWxDdj # 8MPJU8pDkXyi+djJpExPc0hTxJ2qmH0FZtpjKwWnU8dbLSRD9IfYhFK5Tsh1oxYJ # 9Er9ZS0RI2CqK3o2k7keYsJHMaIZbNZKhcoA3XiGs15T9YHe1Rc9FeYDasrQw4wQ # 60FwkA== # =i2CR # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Jul 2022 03:01:52 PM +0530 # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-la-20220704' of https://gitlab.com/rth7680/qemu: (23 commits) target/loongarch: Add lock when writing timer clear reg target/loongarch: Fix the meaning of ECFG reg's VS field hw/rtc/ls7a_rtc: Fix 'calculate' spelling errors hw/rtc/ls7a_rtc: Use tm struct pointer as arguments in toy_time_to_val() hw/rtc/ls7a_rtc: Fix rtc enable and disable function hw/rtc/ls7a_rtc: Add reset function hw/rtc/ls7a_rtc: Remove unimplemented device in realized function hw/rtc/ls7a_rtc: Fix timer call back function hw/rtc/ls7a_rtc: Fix uninitialied bugs and toymatch writing function hw/intc/loongarch_pch_msi: Fix msi vector convertion target/loongarch: Update README default-configs: Add loongarch linux-user support target/loongarch: Adjust functions and structure to support user-mode target/loongarch: remove unused include hw/loader.h target/loongarch: Fix helper_asrtle_d/asrtgt_d raise wrong exception target/loongarch: Fix missing update CSR_BADV target/loongarch: remove badaddr from CPULoongArch scripts: add loongarch64 binfmt config linux-user: Add LoongArch cpu_loop support linux-user: Add LoongArch syscall support ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04Merge tag 'kraxel-20220704-pull-request' of https://gitlab.com/kraxel/qemu ↵Richard Henderson1-5/+26
into staging usb: canokey fixes. ui: better tab labels, cocoa fix, docs: convert fw_cfg to rst. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEoDKM/7k6F6eZAf59TLbY7tPocTgFAmLCndwACgkQTLbY7tPo # cTjNHA/+MT56crVXnjMTdgBRLOuq0cxYnIUptN0JPKx9DTJzdlXEyT+zYD7iIzUt # W0xbOrTLVzU9hfJVh9/5V2HuFmc1eAhfl0BDTzd1TT0kdH6LyUkz5RWgotzo3nvH # 7tnl/sBy48a7diSyQn6K2s8r35ubrX1GNJiJcCLWdVEqvzKKWDEqebs02PxbN/OJ # 9UG9xtkM/QQ1+h74jq5BGKXf08xOhOZIjO274Sn5zievBC9JU6RVkCOlUXiBdk51 # +vNTfKt3c864cstryXSTknYWyVv7zKzCqr7xR7c+fgbt3cN/HmLkM9LGytDMEDl/ # IC0CtKiRN316GgVHHMDT8v8X2dVHNH9ZEEoXRKIbc5jD/tetJw7IIEO7blJphdpV # WE4/bRpJwYVW9UHzig9rPRxsHLs3NSZbNCQEbGUvAbZzS2kq9hnDa/BBtFSYaf+X # RIwR7rY7WhENfSrus1jR5rfWRU7n+q+fcNIFZetUakH1V6Idb0xQir3eM/yM6sBC # nzQSzzLsd3Mwh2ahbnLZ1HkyybZV692usVylKsFLVwcUhCvk+VHccOF31QfrxO/j # ogVzTYYtfrGM5kaknueIMg7XAhjQ04Av70+0b886kZawB3ZE5Ccare2TztHq1jcG # dMdEm7DLaDRm2RXa9NtcbxsIrS0DT2EuFcBnQ1mHMCGql4MidzE= # =Bhbw # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Jul 2022 01:29:24 PM +0530 # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [undefined] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [undefined] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * tag 'kraxel-20220704-pull-request' of https://gitlab.com/kraxel/qemu: hw: canokey: Remove HS support as not compliant to the spec docs/system/devices/usb/canokey: remove limitations on qemu-xhci hw/usb/canokey: fix compatibility of qemu-xhci hw/usb/canokey: Fix CCID ZLP ui/cocoa: Fix clipboard text release ui/console: allow display device to be labeled with given id Convert fw_cfg.rst to reStructuredText syntax Rename docs/specs/fw_cfg.txt to .rst Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04hw/rtc/ls7a_rtc: Fix 'calculate' spelling errorsXiaojuan Yang1-6/+6
Fix 'calculate' spelling errors. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220701093407.2150607-8-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04hw/rtc/ls7a_rtc: Use tm struct pointer as arguments in toy_time_to_val()Xiaojuan Yang1-7/+7
Use pointer as arguments in toy_time_to_val() instead of struct tm. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220701093407.2150607-7-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04hw/rtc/ls7a_rtc: Fix rtc enable and disable functionXiaojuan Yang1-53/+7
Fix ls7a rtc enable and disable function. When rtc disabled, it do not support to read or write, but the real time is still continue, so we need not neither save the time nor update the rtc offset. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220701093407.2150607-6-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04hw/rtc/ls7a_rtc: Add reset functionXiaojuan Yang1-0/+20
Add ls7a rtc reset function to delete timers and clear regs when rtc reset. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Message-Id: <20220701093407.2150607-5-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04hw/rtc/ls7a_rtc: Remove unimplemented device in realized functionXiaojuan Yang1-1/+0
Remove the unimplemented device when realized ls7a RTC, as it is not uesd. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220701093407.2150607-4-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04hw/rtc/ls7a_rtc: Fix timer call back functionXiaojuan Yang1-2/+2
Replace qemu_irq_pulse with qemu_irq_raise in ls7a_timer_cb function to keep consistent with hardware behavior when raise irq. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220701093407.2150607-3-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04hw/rtc/ls7a_rtc: Fix uninitialied bugs and toymatch writing functionXiaojuan Yang1-9/+11
1. Initialize the tm struct in toymatch_write() and ls7a_toy_start() to fix uninitialized bugs. 2. Fix toymatch_val_to_time function. By the document, when we calculate the expiration year, we should first get current year, and replace the 0-5 bits with toymatch's 26-31 bits. Fixes: Coverity CID 1489766, 1489763 Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220701093407.2150607-2-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04hw/intc/loongarch_pch_msi: Fix msi vector convertionMao Bibo2-2/+21
Loongarch pch msi intc connects to extioi controller, the range of irq number is 64-255. Add a property for irqbase, so that we can compute the irq offset from the view of pch_msi controller with the method: msi vector (from view of upper extioi intc) - irqbase Signed-off-by: Mao Bibo <maobibo@loongson.cn> Message-Id: <20220701030740.2469162-1-maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-03hw/riscv: boot: Reduce FDT address alignment constraintsAlistair Francis1-2/+2
We previously stored the device tree at a 16MB alignment from the end of memory (or 3GB). This means we need at least 16MB of memory to be able to do this. We don't actually need the FDT to be 16MB aligned, so let's drop it down to 2MB so that we can support systems with less memory, while also allowing FDT size expansion. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/992 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20220608062015.317894-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-01hw: canokey: Remove HS support as not compliant to the specMkfsSion1-1/+0
Canokey core currently using 16 bytes as maximum packet size for control endpoint, but to run the device in high-speed a 64 bytes maximum packet size is required according to USB 2.0 specification. Since we don't acutally need to run the device in high-speed, simply don't assign high member in USBDesc. When canokey-qemu is used with xhci, xhci would drive canokey in high speed mode, since the bcdUSB in canokey-core is 2.1, yet canokey-core set bMaxPacketSize0 to be 16, this is out of the spec as the spec said that ``The allowable maximum control transfer data payload sizes...for high-speed devices, it is 64 bytes''. In this case, usb device validation in Windows 10 LTSC 2021 as the guest would fail. It would complain USB\DEVICE_DESCRIPTOR_VALIDATION_FAILURE. Note that bcdUSB only identifies the spec version the device complies, but it has no indication of its speed. So it is allowed for the device to run in FS but comply the 2.1 spec. To solve the issue we decided to just drop the high speed support. This only affects usb-ehci as usb-ehci would complain speed mismatch when FS device is attached to a HS port. That's why the .high member was initialized in the first place. Meanwhile, xhci is not affected as it works well with FS device. Since everyone is now using xhci, it does no harm to most users. Suggested-by: Hongren (Zenithal) Zheng <i@zenithal.me> Signed-off-by: YuanYang Meng <mkfssion@mkfssion.com> Reviewed-by: Hongren (Zenithal) Zheng <i@zenithal.me> Message-Id: <20220625142138.19363-1-mkfssion@mkfssion.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2022-07-01hw/usb/canokey: fix compatibility of qemu-xhciHongren (Zenithal) Zheng1-0/+23
XHCI wont poll interrupt IN endpoint if NAKed, and needs wakeup Suggested-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> Message-Id: <YqcqSHNpI7sXRNpZ@Sun> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2022-07-01hw/usb/canokey: Fix CCID ZLPHongren (Zenithal) Zheng1-4/+3
CCID could send zero-length packet (ZLP) if we invoke two data_in, two packets would be concated and we could not distinguish them. The CANOKEY_EMU_EP_CTAPHID is imported from canokey-qemu.h Reported-by: MkfsSion <myychina28759@gmail.com> Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> Message-Id: <YqcqGz0s3+LE42ms@Sun> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2022-06-30hw/misc/aspeed: Add PECI controllerPeter Delevoryas6-1/+199
This introduces a really basic PECI controller that responses to commands by always setting the response code to success and then raising an interrupt to indicate the command is done. This helps avoid getting hit with constant errors if the driver continuously attempts to send a command and keeps timing out. The AST2400 and AST2500 only included registers up to 0x5C, not 0xFC. They supported PECI 1.1, 2.0, and 3.0. The AST2600 and AST1030 support PECI 4.0, which includes more read/write buffer registers from 0x80 to 0xFC to support 64-byte mode. This patch doesn't attempt to handle that, or to create a different version of the controller for the different generations, since it's only implementing functionality that is common to all generations. The basic sequence of events is that the firmware will read and write to various registers and then trigger a command by setting the FIRE bit in the command register (similar to the I2C controller). Then the firmware waits for an interrupt from the PECI controller, expecting the interrupt status register to be filled in with info on what happened. If the command was transmitted and received successfully, then response codes from the host CPU will be found in the data buffer registers. Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220630045133.32251-12-me@pjd.dev> [ clg: s/sysbus_mmio_map/aspeed_mmio_map/ ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30hw/i2c/aspeed: Add new-registers DMA slave mode RX supportPeter Delevoryas1-12/+121
This commit adds support for DMA RX in slave mode while using the new register set in the AST2600 and AST1030. This patch also pretty much assumes packet mode is enabled, I'm not sure if this will work in DMA step mode. This is particularly useful for testing IPMB exchanges between Zephyr and external devices, which requires multi-master I2C support and DMA in the new register mode, because the Zephyr drivers from Aspeed use DMA in the new mode by default. The Zephyr drivers are also using packet mode. The typical sequence of events for receiving data in DMA slave + packet mode is that the Zephyr firmware will configure the slave address register with an address to receive on and configure the bus's function control register to enable master mode and slave mode simultaneously at startup, before any transfers are initiated. RX DMA is enabled in the slave mode command register, and the slave RX DMA buffer address and slave RX DMA buffer length are set. TX DMA is not covered in this patch. When the Aspeed I2C controller receives data from some other I2C master, it will reset the I2CS_DMA_LEN RX_LEN value to zero, then buffer incoming data in the RX DMA buffer while incrementing the I2CC_DMA_ADDR address counter and decrementing the I2CC_DMA_LEN counter. It will also update the I2CS_DMA_LEN RX_LEN value along the way. Once all the data has been received, the bus controller will raise an interrupt indicating a packet command was completed, the slave address matched, a normal stop condition was seen, and the transfer was an RX operation. If the master sent a NACK instead of a normal stop condition, or the transfer timed out, then a slightly different set of interrupt status values would be set. Those conditions are not handled in this commit. The Zephyr firmware then collects data from the RX DMA buffer and clears the status register by writing the PKT_MODE_EN bit to the status register. In packet mode, clearing the packet mode interrupt enable bit also clears most of the other interrupt bits automatically (except for a few bits above it). Note: if the master transmit or receive functions were in use simultaneously with the slave mode receive functionality, then the master mode functions may have raised the interrupt line for the bus before the DMA slave transfer is complete. It's important to have the slave's interrupt status register clear throughout the receive operation, and if the slave attempts to raise the interrupt before the master interrupt status is cleared, then it needs to re-raise the interrupt once the master interrupt status is cleared. (And vice-versa). That's why in this commit, when the master interrupt status is cleared and the interrupt line is lowered, we call the slave interrupt _raise_ function, to see if the interrupt was pending. (And again, vice-versa). Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20220630045133.32251-8-me@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30hw/i2c/aspeed: add slave device in old register modeKlaus Jensen1-9/+80
Add slave mode functionality for the Aspeed I2C controller in old register mode. This is implemented by realizing an I2C slave device owned by the I2C controller and attached to its own bus. The I2C slave device only implements asynchronous sends on the bus, so slaves not supporting that will not be able to communicate with it. Signed-off-by: Klaus Jensen <k.jensen@samsung.com> [ clg: checkpatch fixes ] Message-Id: <20220601210831.67259-6-its@irrelevant.dk> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220630045133.32251-7-me@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30hw/i2c: add asynchronous sendKlaus Jensen8-1/+51
Add an asynchronous version of i2c_send() that requires the slave to explicitly acknowledge on the bus with i2c_ack(). The current master must use the new i2c_start_send_async() to indicate that it wants to do an asynchronous transfer. This allows the i2c core to check if the target slave supports this or not. This approach relies on adding a new enum i2c_event member, which is why a bunch of other devices needs changes in their event handling switches. Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Message-Id: <20220601210831.67259-5-its@irrelevant.dk> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220630045133.32251-6-me@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30hw/i2c: support multiple mastersKlaus Jensen1-1/+33
Allow slaves to master the bus by registering a bottom halve. If the bus is busy, the bottom half is queued up. When a slave has succesfully mastered the bus, the bottom half is scheduled. Signed-off-by: Klaus Jensen <k.jensen@samsung.com> [ clg : - fixed typos in commit log ] Message-Id: <20220601210831.67259-4-its@irrelevant.dk> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220630045133.32251-5-me@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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