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AgeCommit message (Expand)AuthorFilesLines
2021-09-30ipack: Rename ipack_bus_new_inplace() to ipack_bus_init()Peter Maydell2-7/+7
2021-09-30scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named()Peter Maydell12-20/+15
2021-09-30hw/arm: xlnx-zcu102: Add Xilinx eFUSE deviceTong Ho3-0/+45
2021-09-30hw/arm: xlnx-zcu102: Add Xilinx BBRAM deviceTong Ho3-0/+36
2021-09-30hw/arm: xlnx-versal-virt: Add Xilinx eFUSE deviceTong Ho3-0/+92
2021-09-30hw/arm: xlnx-versal-virt: Add Xilinx BBRAM deviceTong Ho3-0/+55
2021-09-30hw/nvram: Introduce Xilinx battery-backed ramTong Ho3-0/+550
2021-09-30hw/nvram: Introduce Xilinx ZynqMP eFuse deviceTong Ho3-0/+861
2021-09-30hw/nvram: Introduce Xilinx Versal eFuse deviceTong Ho4-0/+904
2021-09-30hw/nvram: Introduce Xilinx eFuse QOMTong Ho4-0/+408
2021-09-30allwinner-h3: Switch to SMC as PSCI conduitAlexander Graf1-1/+1
2021-09-29q800: configure nubus available slots for Quadra 800Mark Cave-Ayland1-0/+9
2021-09-29q800: wire up nubus IRQsMark Cave-Ayland1-0/+6
2021-09-29nubus: add support for slot IRQsMark Cave-Ayland2-0/+10
2021-09-29nubus-bridge: make slot_available_mask a qdev propertyMark Cave-Ayland1-0/+7
2021-09-29nubus-bridge: embed the NubusBus object directly within nubus-bridgeMark Cave-Ayland3-6/+8
2021-09-29nubus: move NubusBus from mac-nubus-bridge to nubus-bridgeMark Cave-Ayland3-7/+15
2021-09-29mac-nubus-bridge: rename MacNubusState to MacNubusBridgeMark Cave-Ayland1-3/+5
2021-09-29nubus-bridge: introduce separate NubusBridge structureMark Cave-Ayland1-2/+2
2021-09-29nubus: move nubus to its own 32-bit address spaceMark Cave-Ayland3-7/+36
2021-09-29nubus-device: add romfile property for loading declaration ROMsMark Cave-Ayland1-1/+43
2021-09-29nubus-device: remove nubus_register_rom() and nubus_register_format_block()Mark Cave-Ayland1-143/+0
2021-09-29macfb: don't register declaration ROMMark Cave-Ayland1-6/+0
2021-09-29nubus: generate bus error when attempting to access empty slotsMark Cave-Ayland1-16/+18
2021-09-29nubus: add trace-events for empty slot accessesMark Cave-Ayland3-3/+15
2021-09-29nubus: implement BusClass get_dev_path()Mark Cave-Ayland1-0/+16
2021-09-29nubus: move slot bitmap checks from NubusDevice realize() to BusClass check_a...Mark Cave-Ayland2-21/+29
2021-09-29nubus: use bitmap to manage available slotsMark Cave-Ayland3-7/+31
2021-09-29nubus-device: expose separate super slot memory regionMark Cave-Ayland1-18/+18
2021-09-29nubus-device: rename slot_nb variable to slotMark Cave-Ayland1-7/+7
2021-09-29nubus: add comment indicating reference documentsMark Cave-Ayland1-0/+8
2021-09-27hw/loader: Restrict PC_ROM_* definitions to hw/i386/pcPhilippe Mathieu-Daudé1-0/+6
2021-09-24hw/nvme: Return error for fused operationsPankaj Raghav1-0/+8
2021-09-24hw/nvme: fix verification of select field in namespace attachmentNaveen Nagar1-3/+12
2021-09-24hw/nvme: fix validation of ASQ and ACQKlaus Jensen2-10/+0
2021-09-21Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...Richard Henderson20-565/+1590
2021-09-21Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210921'...Peter Maydell1-2/+3
2021-09-21Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210920' int...Peter Maydell11-76/+524
2021-09-21hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis1-1/+1
2021-09-21hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transferFrank Chang1-6/+6
2021-09-21hw/dma: sifive_pdma: allow non-multiple transaction size transactionsGreen Wan1-6/+10
2021-09-21hw/dma: sifive_pdma: claim bit must be set before DMA transactionsFrank Chang1-0/+9
2021-09-21hw/dma: sifive_pdma: reset Next* registers when Control.claim is setFrank Chang1-0/+19
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel1-1/+112
2021-09-21hw/riscv: virt: Re-factor FDT generationAnup Patel1-200/+327
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel7-138/+303
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel10-15/+15
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis2-1/+55
2021-09-21hw/timer: Add SiFive PWM supportAlistair Francis4-0/+478
2021-09-21hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis2-5/+15
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