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2021-01-19Merge remote-tracking branch ↵Peter Maydell1-82/+157
'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging * Refactor next-cube interrupt and register handling into a proper QOM device # gpg: Signature made Tue 19 Jan 2021 08:15:39 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "huth@tuxfamily.org" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/huth-gitlab/tags/pull-request-2021-01-19: hw/m68k/next-cube: Add missing header comment to next-cube.h hw/m68k/next-cube: Add vmstate for NeXTPC device hw/m68k/next-cube: Remove unused fields from NeXTState hw/m68k/next-cube: Move rtc into NeXTPC struct hw/m68k/next-cube: Make next_irq GPIO inputs to NEXT_PC device hw/m68k/next-cube: Move int_status and int_mask to NeXTPC struct hw/m68k/next-cube: Make next_irq take NeXTPC* as its opaque hw/m68k/next-cube: Move scr_ops into NeXTPC device hw/m68k/next-cube: Move mmio_ops into NeXTPC device hw/m68k/next-cube: Move register/interrupt functionality into a device hw/m68k/next-cube: Make next_irq() function static Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-19hw/m68k/next-cube: Add vmstate for NeXTPC devicePeter Maydell1-1/+33
Add the vmstate for the new NeXTPC devic; this is in theory a migration compatibility break, but this machine doesn't have working migration currently anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-11-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Remove unused fields from NeXTStatePeter Maydell1-4/+0
The fields scsi_irq, scsi_dma, scsi_reset and fd_irq in NeXTState are all unused, except in commented out "this should do something like this" code. Remove the unused fields. As and when the functionality that might use them is added, we can put in the correct kind of wiring (which might or might not need to be a qemu_irq, but which in any case will need to be in the NeXTPC device, not in NeXTState). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-10-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move rtc into NeXTPC structPeter Maydell1-14/+8
Move the rtc into the NeXTPC struct. Since this is the last use of the 'backdoor' NextState pointer we can now remove that. Probably the RTC should be its own device at some point: in hardware there is a separate MCS1850 RTC chip connected to the Peripheral Controller via a 1-bit serial interface. That goes beyond the remit of the current refactoring, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-9-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Make next_irq GPIO inputs to NEXT_PC devicePeter Maydell1-17/+4
Make the next_irq function be GPIO inputs to the NEXT_PC device, rather than a freestanding set of qemu_irq lines. This fixes a minor Coverity issue where it correctly points out the trivial memory leak of the memory allocated in the call to qemu_allocate_irqs(). Fixes: CID 1421962 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-8-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move int_status and int_mask to NeXTPC structPeter Maydell1-17/+16
All the code which accesses int_status and int_mask is now doing so via the NeXTPC->NeXTState indirection, so we can move these fields into the NeXTPC struct where they belong. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-7-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Make next_irq take NeXTPC* as its opaquePeter Maydell1-8/+23
Make the next_irq function take a NeXTPC* as its opaque rather than the M68kCPU*. This will make it simpler to turn the next_irq function into a gpio input line of the NeXTPC device in the next commit. For this to work we have to pass the CPU to the NeXTPC device via a link property, in the same way we do in q800.c (and for the same reason). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-6-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move scr_ops into NeXTPC devicePeter Maydell1-25/+25
Move the registers handled by the scr_ops struct into the NeXTPC device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-5-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move mmio_ops into NeXTPC devicePeter Maydell1-36/+44
Move the registers handled by the mmio_ops struct into the NeXTPC device. This allows us to also move the scr1 and scr2 data fields. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-4-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move register/interrupt functionality into a devicePeter Maydell1-0/+44
Currently the next-cube board code open-codes a lot of handling of interrupts and some miscellaneous registers. Move this into a proper QOM device. In the real hardware this functionality seems to be the responsibility of the Peripheral Controller (PC) chip, so name the device that. There are several different things that will need to be moved into this device: * the mmio_iops register set * the scr_ops register set * the next_irq IRQ handling To ease review, we structure the change as a sequence of commits: in this first commit we create the skeleton of the NeXTPC device with no content, but with a backdoor pointer to the NeXTState machine's state struct so we can move parts of the code and still have refactored and non-refactored code using the same struct data fields. Further commits will move functionality into the new device piece by piece. At the end we will be able to remove the backdoor pointer because all the data fields will be in the NeXTPC struct and not the NeXTState struct. We'll add the VMState for the new device at the end of all that; this is in theory a migration compatibility break but this machine does not currently support migration at all anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-3-peter.maydell@linaro.org> [huth: Add a comment in front of struct NeXTPC] Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Make next_irq() function staticPeter Maydell1-1/+1
The next_irq() function is global, but isn't actually used anywhere outside next-cube.c. Make it static. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-2-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19spapr_cpu_core.c: use g_auto* in spapr_create_vcpu()Daniel Henrique Barboza1-9/+3
Use g_autoptr() with Object and g_autofree with the string to avoid the need of a cleanup path. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210114180628.1675603-6-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-01-19spapr_rtas.c: fix identation of rtas_ibm_suspend_me() argsDaniel Henrique Barboza1-3/+3
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210114180628.1675603-5-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-01-19spapr_hcall.c: make do_client_architecture_support staticDaniel Henrique Barboza1-0/+1
The function is called only inside spapr_hcall.c. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210114180628.1675603-3-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-01-19spapr: Improve handling of memory unplug with old guestsGreg Kurz3-13/+21
Since commit 1e8b5b1aa16b ("spapr: Allow memory unplug to always succeed") trying to unplug memory from a guest that doesn't support it (eg. rhel6) no longer generates an error like it used to. Instead, it leaves the memory around : only a subsequent reboot or manual use of drmgr within the guest can complete the hot-unplug sequence. A flag was added to SpaprMachineClass so that this new behavior only applies to the default machine type. We can do better. CAS processes all pending hot-unplug requests. This means that we don't really care about what the guest supports if the hot-unplug request happens before CAS. All guests that we care for, even old ones, set enough bits in OV5 that lead to a non-empty bitmap in spapr->ov5_cas. Use that as a heuristic to decide if CAS has already occured or not. Always accept unplug requests that happen before CAS since CAS will process them. Restore the previous behavior of rejecting them after CAS when we know that the guest doesn't support memory hot-unplug. This behavior is suitable for all machine types : this allows to drop the pre_6_0_memory_unplug flag. Fixes: 1e8b5b1aa16b ("spapr: Allow memory unplug to always succeed") Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <161012708715.801107.11418801796987916516.stgit@bahia.lan> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-01-19sam460ex: Use type cast macro instead of simple castBALATON Zoltan1-5/+2
Use the PCI_BUS type cast macro to convert result of qdev_get_child_bus(). Also remove the check for NULL afterwards which should not be needed because sysbus_create_simple() uses error_abort and we create the PCI host object here that's expected to have a PCI bus so this shouldn't fail. Even if it would fail that would be due to a programmer error so an error message is not necessary. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <a4dc55b56eed3ce899b7bf9835b980a114c52598.1610143658.git.balaton@eik.bme.hu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-01-19Revert "ppc4xx: Move common dependency on serial to common option"BALATON Zoltan1-1/+4
This reverts commit e6d5106786 which was added mistakenly. While this change works it was suggested during review that keeping dependencies explicit for each board may be better than listing them in a common option so keep the previous version and revert this change. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <8c65807fc7dc1c4c4f6320f2fd6409a3091c88ff.1610143658.git.balaton@eik.bme.hu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-01-19Revert "sam460ex: Remove FDT_PPC dependency from KConfig"BALATON Zoltan1-0/+1
This reverts commit 038da2adf that was mistakenly added, this dependency is still needed to get libfdt dependencies even if fdt.o is not needed by sam460ex. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <15a9fa72eed4f02bdbeaef206803d5e22260e2de.1610143658.git.balaton@eik.bme.hu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-01-19hw/ppc: Remove unused ppcuic_init()Peter Maydell1-38/+0
Now we've converted all the callsites to directly create the QOM UIC device themselves, the ppcuic_init() function is unused and can be removed. The enum defining PPCUIC symbolic constants can be moved to the ppc-uic.h header where it more naturally belongs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20210108171212.16500-5-peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-01-19hw/ppc/ppc405_uc: Drop use of ppcuic_init()Peter Maydell3-33/+47
Switch the ppc405_uc boards to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. We retain the API feature of ppc405ep_init() where it passes back something allowing the callers to wire up devices to the UIC if they need to, even though neither of the callsites currently makes use of this ability -- instead of passing back the qemu_irq array we pass back the UIC DeviceState. This fixes a trivial Coverity-detected memory leak where we were leaking the array of IRQs returned by ppcuic_init(). Fixes: Coverity CID 1421922 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210108171212.16500-4-peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-01-19hw/intc/ppc-uic: Make default dcr-base 0xc0, not 0x30Peter Maydell1-1/+1
In commit 34d0831f38fd8 the ppc-uic device was added, with a dcr-base property. The intention was that the default value of dcr-base should be the one that most of our boards need, so that in the common case they don't need to specify a property value. All QEMU boards with a UIC use a dcr-base of 0xc0, with the exception of sam460ex which has four UICs and so puts them at 0xc0, 0xd0, 0xe0, 0xf0. So 0xc0 is the obvious right choice for the default dcr-base. The board code conversions in commits 0270d74ef88623505 (bamboo) and c5ac9dc64fa552a6 (virtex_ml507) assumed that default was 0xc0. Unfortunately the actual default in 34d0831f38fd8 was 0x30, by mistake, so the bamboo and virtex_ml507 boards were broken as they were converted away from ppcuic_init() (which always specifies the dcr_base property value explicitly). Set the default dcr-base to 0xc0 as was intended, fixing bamboo and virtex_ml507. Fixes: 34d0831f38fd8 Reported-by: Nathan Chancellor <natechancellor@gmail.com> Suggested-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210111213007.7381-1-peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-01-19hw/ppc: Delete unused ppc405cr_init() codePeter Maydell2-351/+0
The function ppc405cr_init() has apparently been unused since it was added in commit 8ecc7913525ecb in 2007. Remove this dead code, so we don't have to convert it away from using ppcuic_init(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210108171212.16500-3-peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-01-19hw/ppc/sam460ex: Drop use of ppcuic_init()Peter Maydell1-16/+53
Switch the sam460ex board to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210108171212.16500-2-peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-01-18Merge remote-tracking branch ↵Peter Maydell4-5/+26
'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging Trivial patches 20210118 Fix memory leaks Use qemu_log_mask(GUEST_ERROR) rather than error_report(). # gpg: Signature made Mon 18 Jan 2021 11:31:10 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.0-pull-request: hw/ide/ahci: Replace fprintf() by qemu_log_mask(GUEST_ERROR) misc/mos6522: Use timer_free() in the finalize function to avoid memleak pl031: Use timer_free() in the finalize function to avoid memleaks hw/virtio-pci: Replace error_report() by qemu_log_mask(GUEST_ERROR) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-18Merge remote-tracking branch ↵Peter Maydell4-0/+1352
'remotes/stsquad/tags/pull-testing-and-misc-180121-2' into staging Testing, gdbstub and semihosting patches: - clean-ups to docker images - drop duplicate jobs from shippable - prettier tag generation (+gtags) - generate browsable source tree - more Travis->GitLab migrations - fix checkpatch to deal with commits - gate gdbstub tests on 8.3.1, expand tests - support Xfer:auxv:read gdb packet - better gdbstub cleanup - use GDB's SVE register layout - make arm-compat-semihosting common - add riscv semihosting support - add HEAPINFO, ELAPSED, TICKFREQ, TMPNAM and ISERROR to semihosting # gpg: Signature made Mon 18 Jan 2021 10:09:11 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-and-misc-180121-2: (30 commits) semihosting: Implement SYS_ISERROR semihosting: Implement SYS_TMPNAM semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ riscv: Add semihosting support for user mode riscv: Add semihosting support semihosting: Support SYS_HEAPINFO when env->boot_info is not set semihosting: Change internal common-semi interfaces to use CPUState * semihosting: Change common-semi API to be architecture-independent semihosting: Move ARM semihosting code to shared directories target/arm: use official org.gnu.gdb.aarch64.sve layout for registers gdbstub: ensure we clean-up when terminated gdbstub: drop gdbserver_cleanup in favour of gdb_exit gdbstub: drop CPUEnv from gdb_exit() gdbstub: add support to Xfer:auxv:read: packet gdbstub: implement a softmmu based test Revert "tests/tcg/multiarch/Makefile.target: Disable run-gdbstub-sha1 test" configure: gate our use of GDB to 8.3.1 or above test/guest-debug: echo QEMU command as well scripts/checkpatch.pl: fix git-show invocation to include diffstat gitlab: migrate the minimal tools and unit tests from Travis ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # default-configs/targets/riscv32-linux-user.mak # default-configs/targets/riscv64-linux-user.mak
2021-01-18hw/ide/ahci: Replace fprintf() by qemu_log_mask(GUEST_ERROR)Philippe Mathieu-Daudé1-3/+5
Replace fprintf() calls by qemu_log_mask(LOG_GUEST_ERROR). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210112112955.1849212-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-18misc/mos6522: Use timer_free() in the finalize function to avoid memleakGan Qixin1-0/+9
When running device-introspect-test, a memory leak occurred in the mos6522_init function, this patch use timer_free() in the finalize function to fix it. ASAN shows memory leak stack: Direct leak of 96 byte(s) in 2 object(s) allocated from: #0 0xfffd5fe9e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) #1 0xfffd5f7b6800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) #2 0xaaae50303d0c in timer_new_full qemu/include/qemu/timer.h:523 #3 0xaaae50303d0c in timer_new qemu/include/qemu/timer.h:544 #4 0xaaae50303d0c in timer_new_ns qemu/include/qemu/timer.h:562 #5 0xaaae50303d0c in mos6522_init qemu/hw/misc/mos6522.c:490 #6 0xaaae50b77d70 in object_init_with_type qemu/qom/object.c:371 #7 0xaaae50b7ae84 in object_initialize_with_type qemu/qom/object.c:515 #8 0xaaae50b7b0f8 in object_new_with_type qemu/qom/object.c:729 #9 0xaaae50bb6d58 in qmp_device_list_properties qemu/qom/qom-qmp-cmds.c:153 #10 0xaaae50d7e1dc in qmp_marshal_device_list_properties qemu/qapi/qapi-commands-qdev.c:59 #11 0xaaae50dc87a0 in do_qmp_dispatch_bh qemu/qapi/qmp-dispatch.c:110 #12 0xaaae50d931a0 in aio_bh_call qemu/util/async.c:136 Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Gan Qixin <ganqixin@huawei.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210112112705.380534-3-ganqixin@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-18pl031: Use timer_free() in the finalize function to avoid memleaksGan Qixin1-0/+8
When running device-introspect-test, a memory leak occurred in the pl031_init function, this patch use timer_free() in the finalize function to fix it. ASAN shows memory leak stack: Direct leak of 48 byte(s) in 1 object(s) allocated from: #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) #2 0xaaabf5621cfc in timer_new_full qemu/include/qemu/timer.h:523 #3 0xaaabf5621cfc in timer_new qemu/include/qemu/timer.h:544 #4 0xaaabf5621cfc in timer_new_ns qemu/include/qemu/timer.h:562 #5 0xaaabf5621cfc in pl031_init qemu/hw/rtc/pl031.c:194 #6 0xaaabf6339f6c in object_initialize_with_type qemu/qom/object.c:515 #7 0xaaabf633a1e0 in object_new_with_type qemu/qom/object.c:729 #8 0xaaabf6375e40 in qmp_device_list_properties qemu/qom/qom-qmp-cmds.c:153 #9 0xaaabf5a95540 in qdev_device_help qemu/softmmu/qdev-monitor.c:283 #10 0xaaabf5a96940 in qmp_device_add qemu/softmmu/qdev-monitor.c:801 #11 0xaaabf5a96e70 in hmp_device_add qemu/softmmu/qdev-monitor.c:916 #12 0xaaabf5ac0a2c in handle_hmp_command qemu/monitor/hmp.c:1100 Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Gan Qixin <ganqixin@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210112112705.380534-2-ganqixin@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-18hw/virtio-pci: Replace error_report() by qemu_log_mask(GUEST_ERROR)Philippe Mathieu-Daudé1-2/+4
Replace I/O write error reported with error_report() by qemu_log_mask(GUEST_ERROR) which allow filtering. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20201210172834.178052-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-18Merge remote-tracking branch ↵Peter Maydell6-36/+119
'remotes/alistair/tags/pull-riscv-to-apply-20210117-3' into staging First RISC-V PR for 6.0 This PR: - Fixes some issues with the m25p80 - Improves GDB support for RISC-V - Fixes some Linux boot issues, specifiaclly 32-bit boot failures - Enforces PMP exceptions correctly - Fixes some Coverity issues # gpg: Signature made Sun 17 Jan 2021 21:53:19 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210117-3: riscv: Pass RISCVHartArrayState by pointer target/riscv: Remove built-in GDB XML files for CSRs target/riscv: Generate the GDB XML file for CSR registers dynamically target/riscv: Add CSR name in the CSR function table target/riscv: Make csr_ops[CSR_TABLE_SIZE] external hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type target/riscv/pmp: Raise exception if no PMP entry is configured RISC-V: Place DTB at 3GB boundary instead of 4GB gdb: riscv: Add target description hw/block: m25p80: Implement AAI-WP command support for SST flashes hw/block: m25p80: Don't write to flash if write is disabled Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-18semihosting: Implement SYS_ISERRORKeith Packard1-0/+4
Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210107170717.2098982-10-keithp@keithp.com> Message-Id: <20210108224256.2321-21-alex.bennee@linaro.org>
2021-01-18semihosting: Implement SYS_TMPNAMKeith Packard1-2/+19
Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210107170717.2098982-9-keithp@keithp.com> Message-Id: <20210108224256.2321-20-alex.bennee@linaro.org>
2021-01-18semihosting: Implement SYS_ELAPSED and SYS_TICKFREQKeith Packard1-0/+16
These are part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210107170717.2098982-8-keithp@keithp.com> Message-Id: <20210108224256.2321-19-alex.bennee@linaro.org>
2021-01-18riscv: Add semihosting supportKeith Packard2-2/+85
Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-6-keithp@keithp.com> Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org>
2021-01-18semihosting: Support SYS_HEAPINFO when env->boot_info is not setKeith Packard1-1/+42
env->boot_info is only set in some ARM startup paths, so we cannot rely on it to support the SYS_HEAPINFO semihosting function. When not available, fallback to finding a RAM memory region containing the current stack and use the base of that. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210107170717.2098982-5-keithp@keithp.com> Message-Id: <20210108224256.2321-16-alex.bennee@linaro.org>
2021-01-18semihosting: Change internal common-semi interfaces to use CPUState *Keith Packard1-163/+186
This makes all of the internal interfaces architecture-independent and renames the internal functions to use the 'common_semi' prefix instead of 'arm' or 'arm_semi'. To do this, some new architecture-specific internal helper functions were created: static inline target_ulong common_semi_arg(CPUState *cs, int argno) Returns the argno'th semihosting argument, where argno can be either 0 or 1. static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) Sets the semihosting return value. static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr) This detects whether the specified semihosting call, which is either TARGET_SYS_EXIT or TARGET_SYS_EXIT_EXTENDED should be executed using the TARGET_SYS_EXIT_EXTENDED semantics. static inline target_ulong common_semi_rambase(CPUState *cs) Returns the base of RAM region used for heap and stack. This is used to construct plausible values for the SYS_HEAPINFO call. In addition, several existing functions have been changed to flag areas of code which are architecture specific: static target_ulong common_semi_flen_buf(CPUState *cs) Returns the current stack pointer minus 64, which is where a stat structure will be placed on the stack #define GET_ARG(n) This fetches arguments from the semihosting command's argument block. The address of this is available implicitly through the local 'args' variable. This is *mostly* architecture independent, but does depend on the current ABI's notion of the size of a 'long' parameter, which may need run-time checks (as it does on AARCH64) #define SET_ARG(n, val) This mirrors GET_ARG and stores data back into the argument block. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-4-keithp@keithp.com> Message-Id: <20210108224256.2321-15-alex.bennee@linaro.org>
2021-01-18semihosting: Change common-semi API to be architecture-independentKeith Packard2-6/+46
The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-3-keithp@keithp.com> Message-Id: <20210108224256.2321-14-alex.bennee@linaro.org>
2021-01-18semihosting: Move ARM semihosting code to shared directoriesKeith Packard3-0/+1128
This commit renames two files which provide ARM semihosting support so that they can be shared by other architectures: 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c 2. linux-user/arm/semihost.c -> linux-user/semihost.c The build system was modified use a new config variable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> [AJB: rename arm-compat-semi, select SEMIHOSTING] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210107170717.2098982-2-keithp@keithp.com> Message-Id: <20210108224256.2321-13-alex.bennee@linaro.org>
2021-01-17Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell7-36/+90
pc,pci,virtio: fixes, features Fixes all over the place. PXB support for ARM. boot index for vhost-user-fs. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 17 Jan 2021 11:44:55 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: acpi: Update _DSM method in expected files acpi: Enable pxb unit-test for ARM virt machine Kconfig: Compile PXB for ARM_VIRT acpi/gpex: Exclude pxb's resources from PCI0 acpi/gpex: Inform os to keep firmware resource map acpi: Add addr offset in build_crs acpi: Fix unmatched expected DSDT.pxb file acpi: Allow DSDT acpi table changes vhost-user-fs: add the "bootindex" property pci/shpc: don't push attention button when ejecting powered-off device Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-17Kconfig: Compile PXB for ARM_VIRTJiahui Cen1-1/+1
PXB is now supported on ARM, so let's compile for arm_virt machine. Acked-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com> Message-Id: <20210114100643.10617-7-cenjiahui@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-01-17acpi/gpex: Exclude pxb's resources from PCI0Jiahui Cen1-21/+43
Exclude the resources of extra root bridges from PCI0's _CRS. Otherwise, the resource windows would overlap in guest, and the IO resource window would fail to be registered. Acked-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com> Message-Id: <20210114100643.10617-6-cenjiahui@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-01-17acpi/gpex: Inform os to keep firmware resource mapJiahui Cen1-2/+18
There may be some differences in pci resource assignment between guest os and firmware. Eg. A Bridge with Bus [d2] -+-[0000:d2]---01.0-[d3]----01.0 where [d2:01.00] is a pcie-pci-bridge with BAR0 (mem, 64-bit, non-pref) [size=256] [d3:01.00] is a PCI Device with BAR0 (mem, 64-bit, pref) [size=128K] BAR4 (mem, 64-bit, pref) [size=64M] In EDK2, the Resource Map would be: PciBus: Resource Map for Bridge [D2|01|00] Type = PMem64; Base = 0x8004000000; Length = 0x4100000; Alignment = 0x3FFFFFF Base = 0x8004000000; Length = 0x4000000; Alignment = 0x3FFFFFF; Owner = PCI [D3|01|00:20] Base = 0x8008000000; Length = 0x20000; Alignment = 0x1FFFF; Owner = PCI [D3|01|00:10] Type = Mem64; Base = 0x8008100000; Length = 0x100; Alignment = 0xFFF It would use 0x4100000 to calculate the root bus's PMem64 resource window. While in Linux, kernel will use 0x1FFFFFF as the alignment to calculate the PMem64 size, which would be 0x6000000. So kernel would try to allocate 0x6000000 from the PMem64 resource window, but since the window size is 0x4100000 as assigned by EDK2, the allocation would fail. The diffences could result in resource assignment failure. Using _DSM #5 method to inform guest os not to ignore the PCI configuration that firmware has done at boot time could handle the differences. Acked-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com> Message-Id: <20210114100643.10617-5-cenjiahui@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-01-17acpi: Add addr offset in build_crsJiahui Cen3-10/+14
AML needs Address Translation offset to describe how a bridge translates addresses accross the bridge when using an address descriptor, and especially on ARM, the translation offset of pio resource is usually non zero. Therefore, it's necessary to pass offset for pio, mmio32, mmio64 and bus number into build_crs. Acked-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com> Message-Id: <20210114100643.10617-4-cenjiahui@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis4-19/+17
We were accidently passing RISCVHartArrayState by value instead of pointer. The type is 824 bytes long so let's correct that and pass it by pointer instead. Fixes: Coverity CID 1438099 Fixes: Coverity CID 1438100 Fixes: Coverity CID 1438101 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
2021-01-16hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwriteGreen Wan1-8/+23
Fix code coverage issues by checking return value and handling fail case of blk_pread() and blk_pwrite(). Return default value 0xff if read fails. Fixes: Coverity CID 1435959 Fixes: Coverity CID 1435960 Fixes: Coverity CID 1435961 Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201104092900.21214-1-green.wan@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-01-16hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng1-5/+1
SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence there is no need to use #idef to set the mc->default_cpu_type. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210109143637.29645-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-01-16RISC-V: Place DTB at 3GB boundary instead of 4GBAtish Patra1-4/+4
Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is lesser. However, Linux kernel can address only 1GB of memory for RV32. Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address). As a result, it can not process DT and panic if opensbi dynamic firmware is used. While at it, place the DTB further away to avoid in memory placement issues in future. Fix this by placing the DTB at 16MB from 3GB or end of DRAM whichever is lower. Fixes: 66b1205bc5ab ("RISC-V: Copy the fdt in dram instead of ROM") Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Message-id: 20210107091127.3407870-1-atish.patra@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-01-16hw/block: m25p80: Implement AAI-WP command support for SST flashesXuzhou Cheng1-0/+73
Auto Address Increment (AAI) Word-Program is a special command of SST flashes. AAI-WP allows multiple bytes of data to be programmed without re-issuing the next sequential address location. Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-id: 1608688825-81519-2-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-01-16hw/block: m25p80: Don't write to flash if write is disabledBin Meng1-0/+1
When write is disabled, the write to flash should be avoided in flash_write8(). Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI flash device") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-id: 1608688825-81519-1-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-01-15Merge remote-tracking branch 'remotes/gkurz-gitlab/tags/9p-next-2021-01-15' ↵Peter Maydell1-3/+3
into staging Fix for CVE-2021-20181 # gpg: Signature made Fri 15 Jan 2021 08:52:19 GMT # gpg: using RSA key B4828BAF943140CEF2A3491071D4D5E5822F73D6 # gpg: Good signature from "Greg Kurz <groug@kaod.org>" [full] # gpg: aka "Gregory Kurz <gregory.kurz@free.fr>" [full] # gpg: aka "[jpeg image of size 3330]" [full] # Primary key fingerprint: B482 8BAF 9431 40CE F2A3 4910 71D4 D5E5 822F 73D6 * remotes/gkurz-gitlab/tags/9p-next-2021-01-15: 9pfs: Fully restart unreclaim loop (CVE-2021-20181) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-01-08 17:14:04 +0000