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2008-12-18Fix warnings introduced by commit 6081aurel322-3/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6084 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-17Add HPET emulation to qemu (Beth Kon)aliguori7-5/+732
This patch adds HPET emulation. It can be disabled with -disable-hpet. An hpet provides a more finely granular clocksource than otherwise available on PC. This means that latency-dependent applications (e.g. multimedia) will generally be smoother when using the HPET. Signed-off-by: Beth Kon <eak@us.ibm.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6081 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-17Handle suspend in qemu (Gleb Natapov)aliguori3-0/+32
Reset a PC and tell BIOS that resume from ram is required on the next boot. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6080 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-17Use saner types for virtio-netaliguori1-2/+2
This was spotted by malc Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6075 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-17virtio-net supportaliguori3-1/+413
This adds virtio-net support. This is based on the virtio-net driver that exists in kvm-userspace. This also adds a new qemu_sendv_packet which virtio-net requires. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6073 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-16target-ppc: IBM PowerPC 440EP Bamboo reference board emulationaurel322-0/+191
Since most IO devices are integrated into the 440EP chip, "Bamboo support" mostly entails implementing the -kernel, -initrd, and -append options. These options are implemented by loading the guest as if u-boot had done it, i.e. loading a flat device tree, updating it to hold initrd addresses, ram size, and command line, and passing the FDT address in r3. Since we use it with KVM, we enable the virtio block driver and include hooks necessary for KVM support. Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6067 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-16target-ppc: PowerPC 440EP SoC emulationaurel322-0/+123
Wire up the system-on-chip devices present on 440EP chips. This patch is a little unusual in that qemu doesn't actually emulate the 440 core, but we use this board code with KVM (which does). If/when 440 core emulation is supported, the kvm_enabled() hack can be removed. Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6066 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15target-ppc: create a helper function to allow more flexible RAM allocation ↵aurel322-0/+47
for PPC 4xx The 4xx SDRAM controller supports a small number of banks, and each bank must be one of a small set of sizes. The number of banks and the supported sizes varies by SoC. This function uses the user-specified RAM size to fill in the "ram_bases" and "ram_sizes" arrays required by ppc4xx_sdram_init(). Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6063 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15target-ppc: rename ppc405_sdram_init() to ppc4xx_sdram_init()aurel323-4/+4
The SDRAM controller is shared across almost all 405 and 440 embedded processors, with some slight differences such as the sizes supported for each memory bank. Rename only; no functional changes. Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6062 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15target-ppc: move PPC4xx SDRAM controller emulation from ppc405_uc.c to ↵aurel324-346/+346
ppc4xx_devs.c The SDRAM controller is shared across almost all 405 and 440 embedded processors, with some slight differences such as the sizes supported for each memory bank. Code movement only; no functional changes. Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6061 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15Revert part of r5853blueswir11-2/+5
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6057 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15ARM: basic SX1-cellphone sysemu support (Jean-Christophe PLAGNIOL-VILLARD).balrog2-0/+242
The TSC2102 chip is not included in documentation because a patch is pending. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6038 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15Fix the PXA2xx LCD dirty page detection a little more.balrog1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6037 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13Fix PXA2xx framebuffer dirty checking.balrog1-2/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6019 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13Remove unnecessary trailing newlinesblueswir134-38/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11PPC405EP: fix fpga write functionaurel321-3/+3
I'm not familiar with this device, but I'm fairly certain the writel handler is not supposed to recurse. Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5995 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11baum: remove 2 warningsaurel321-0/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5994 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11pci: virtio: use pci id defines (Gerd Hoffman)aliguori4-8/+8
Use the defines added by the previous patch in the virtio drivers. Also remove the pointless vendor and device args from the virtio_blk_init() function. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5987 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11pci: add default pci subsystem id for all devices (Gerd Hoffman)aliguori2-0/+25
This sets a default PCI subsystem ID for all emulated PCI devices. PCI specs require this, so do it. In many cases it is enougth to know the PCI ID to handle a device correctly. Sometimes a device driver must identify the exact piece of hardware (via PCI Subsystem ID) though. What does this patch to qemu devices: Right now the emulated PCI devices have no PCI subsystem ID, only the PCI ID. The discussed patch sets a default PCI subsystem ID for all emulated devices. Which will make the qemu devices look pretty much like in the laptop case: all PCI subsystem IDs will point to qemu by default. If a driver emulates a very specific piece of hardware where it has to emulate more than just the PCI chip, it can overwrite the PCI subsystem ID without problems. The es1370 driver does that for example. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5986 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11Rename fls to qemu_flsblueswir11-1/+1
Fix compiler warning on OSX, reported by Andreas Faerber. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5982 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11Allow to register a callback with fw_cfg_add_callback()blueswir11-2/+4
fw_cfg_add_callback() checks if key has FW_CFG_WRITE_CHANNEL bit set after masking the key with FW_CFG_ENTRY_MASK. But as FW_CFG_ENTRY_MASK is ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL), the bit is never set and function exits. This patch corrects this by checking the bit before masking the value. Signed-by-off: Laurent Vivier <Laurent.Vivier@bull.net> Acked-by: Gleb Natapov <gleb@redhat.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5978 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11Add missing static qualifiermalc1-3/+3
Caught by -Wstrict-prototypes git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5975 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10IDE: Implement SEEK commandaurel321-0/+7
Signed-off-by: Justin Chevrier <theburner1@yahoo.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5972 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10Add 64-bit Block Move support (Direct & Table Indirect) (Ryan Harper)aliguori1-3/+60
This patch adds support for 64-bit Block Move instructions. There are multiple modes for 64-bit Block moves, direct, indirect, and table indirect. This patch implements Direct and Table indirect moves which are needed by 64-bit windows and SYM_CONF_DMA_ADDRESSING_MODE=2 for the Linux sym53c8xx_2 driver respectively. Two helper functions are included to check which mode the guest is using. For 64-bit direct moves, we fetch a 3rd DWORD and store the value in the DBMS register. For Table Indirect moves, we look into the table for which register contains the upper 32-bits of the 64-bit address. This selector value indicates which register to pull the value from and into dnad64 register. Finally, lsi_do_dma is updated to use the approriate register to build a 64-bit DMA address if required. With this patch, Windows XP x64, 2003 SP2 x64, can now install to scsi devices. Linux SYM_CONF_DMA_ADDRESSING_MODE=2 need a quirk fixup in Patch 4 to function properly. Signed-off-by: Ryan Harper <ryanh@us.ibm.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5969 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10LSI53C895A: Rename dmbs register to dbms (Ryan Harper)aliguori1-4/+4
Register name should be: Dynamic Block Move Selector (dbms) according to page 215 of the LSI 53C895A Technical Manual[1]. 1. http://www.lsi.com/DistributionSystem/AssetDocument/files/docs/techdocs/storage_stand_prod/SCSIControllers/lsi53c895a_tech_manual.pdf Signed-off-by: Ryan Harper <ryanh@us.ibm.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5968 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10MIPS Magnum: fix memory-mapped i8042aurel323-20/+14
Current implementation of memory-mapped i8042 controller is atm implemented with an interface shift (it_shift) parameter, like most all memory-mapped devices in Qemu. However, this isn't suitable for MIPS Magnum, where i8042 controller is at 0x80005000 up to 0x80005fff. Thomas Bogendoerfer (from #mipslinux) tested the behaviour of a real machine, and found that odd addresses are for status/command register, and even addresses for data register. Attached patch implements this behaviour by replacing the it_shift parameter by a mask one. Incidentally, keyboard now works on OpenBSD 2.3, which accesses i8042 controller at 0x80005060 and 0x80005061. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5962 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-09KVM: Coalesced MMIO supportaliguori4-0/+16
MMIO exits are more expensive in KVM or Xen than in QEMU because they involve, at least, privilege transitions. However, MMIO write operations can be effectively batched if those writes do not have side effects. Good examples of this include VGA pixel operations when in a planar mode. As it turns out, we can get a nice boost in other areas too. Laurent mentioned a 9.7% performance boost in iperf with the coalesced MMIO changes for the e1000 when he originally posted this work for KVM. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5961 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07Move spitz microdrive to PCMCIA socket 0.balrog1-5/+5
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5946 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07MIPS: remove a few warningsaurel323-2/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5944 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07Parallel port resetaurel321-5/+11
Attached patch adds a reset handler to parallel port, so it gets correct register values after a reset. (Hervé Poussineau) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5942 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07target-ppc: kill a few warningsaurel321-0/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5941 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH4: SCI improvementaurel321-6/+6
This patch simply implement one register of SH4's SCI := Serial Communication Interface. R2D evaluation board uses SCI for SPI connection. So, Linux kernel for R2D with default configuration causes a QEMU assertion failure when it initializes SPI driver. This patch avoids it and reduces the kernel config modification work for QEMU. Completing SCI implementation task is left. Other board support is desirable to confirm this task, which uses SCI for a serial terminal. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5939 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH4: kill a few warningsaurel325-3/+9
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5938 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).balrog5-4/+18
Main purpose of this is to delete *physical = address & 0x1fffffff; at target-sh4/helper.c:449, using new mmio rule introduced by #5849 This masking is a nice trick to realize P4/A7 duality of SH registers. But, IMHO, it is logically wrong. Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have one more address called A7 which is usually P4 address with upper 3bits masked. This is an address only appears in TLB's physical address part. Current code use trick writing drivers as if they are really in A7 (that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5935 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH: improve the way sh7750 registers io memory (Takashi YOSHII).balrog2-55/+41
Fixes to be needed for commit #5849 "Change MMIO callbacks..." hw/sh7750.c: - Divide region of CPU control registers to avoid overlapping to peripheral modules. - Delete unused var "icr", which had moved to hw/sh_intc.c. hw/sm501.c: - Merge non page aligned palette registers into the region of control registers. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5934 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07Fix some new warnings introduced after r5022blueswir11-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5933 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH: r2d pci support (Takashi YOSHII).balrog2-0/+44
This patch adds pci support to sh/r2d board. This is the first user of PCIC support I formerly sent. PCIC actually is inside of chip with CPU core on SH7751. But, this code is written as if SH7750 and PCIC are on board. I care little about physical device boundary, but fitting with qemu's design. This patch also adds some BSC (Bus State Controller) registers, because PCI device driver software have to accesses them. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5932 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH: Don't subtract bases from access addresses in PCIC.balrog1-5/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5928 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH: On-chip PCI controller support (Takashi YOSHII).balrog1-0/+207
This patch adds SuperH on-chip PCI controller(PCIC) support. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5927 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07sh4: Add r2d onboard FPGA IRQ controller (Takashi YOSHII).balrog1-5/+63
This adds IRQ controller in FPGA on r2d, and use it for CF. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5926 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07sh4: Add IRL (4-bit encoded interrupt input) support (Takashi YOSHII).balrog4-1/+59
This patch adds IRL(4bit encoded 15 level interrupt input) support to SH using qemu_irq as a multi level (!=on/off) signal. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5925 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07sh4: mmio based CF support on r2d board (Takashi YOSHII).balrog3-0/+101
This patch adds emulation for a CompactFlash on sh4/r2d board. The device is CF, but wired to be worked as True-IDE mode, and connected directly to SH bus. So, this code is to support generally mmio based IDEs which are supported by "pata_platform" driver in linux kernel. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5924 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07PXA: Account for offset from page start in a subpage mapping.balrog1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5917 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07omap1: fix uart3 init (Jean-Christophe PLAGNIOL-VILLARD).balrog1-1/+1
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5906 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07omap1: add OSC_12M_SEL UART register support (original patch from ↵balrog1-10/+17
Jean-Christophe PLAGNIOL-VILLARD) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5905 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07pflash_cfi01: add Single Byte Program (Jean-Christophe PLAGNIOL-VILLARD).balrog1-34/+53
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5904 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SCSI: Handle inquiry commands of varying length (Justin Chevrier).balrog1-3/+8
Openserver 5.0.5 sends an Inquiry command to the emulated SCSI disk expecting a response length of 40 bytes. Currently the response to an Inquiry command is hardcoded to 36 bytes. When receiving a response of length 36 instead of 40 Openserver panics. Modifications to original patch based on feedback from Ryan Harper and Paul Brook. Thanks guys. Signed-off-by: Justin Chevrier <address@hidden> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5903 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07LSI53C895A: Handle empty SCRIPTS opcode (Justin Chevrier)balrog1-0/+6
Basically after each DMA transfer the Openserver driver would issue an empty (0) SCRIPTS opcode. As the opcode is essentially a NOP it has no second DWORD and therefore the DSP should only be incremented by 4 bytes instead of the 8 bytes we currently do. Here's a snippet of the log: lsi_scsi: Data ready tag=0x100d9 len=16384 ... lsi_scsi: SCRIPTS dsp=068c5e50 opcode 01000400 arg 07a09000 lsi_scsi: DMA addr=0x07a09000 len=1024 lsi_scsi: SCRIPTS dsp=068c5e58 opcode 00000000 arg 01000400 lsi_scsi: Wrong phase got 1 expected 0 Note the 2nd DWORD after the empty opcode; the next opcode in the DMA transfer sequence. As can be expected the address after that has the next DMA address to use. After the attached patch the DMA transfer is able to complete successfully: lsi_scsi: SCRIPTS dsp=068c5e50 opcode 01000400 arg 07a0d000 lsi_scsi: DMA addr=0x07a0d000 len=1024 lsi_scsi: SCRIPTS dsp=068c5e5c opcode 01000400 arg 07a0d400 lsi_scsi: DMA addr=0x07a0d400 len=1024 ... Tested againsted Openserver 5.0.5 and Debian ARM. Signed-off-by: Justin Chevrier <address@hidden> Acked-by: Ryan Harper <ryanh@us.ibm.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5902 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07LSI53C895A: Remove current_dma_len hackbalrog1-1/+0
Signed-off-by: Justin Chevrier <address@hidden> Acked-by: Ryan Harper <ryanh@us.ibm.com> Acked-by: Chris Wright <chrisw@sous-sol.org> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5901 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07Remove a duplicate omap_l4_attach(), add one missing elsewhere.balrog2-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5900 c046a42c-6fe2-441c-8c8c-71466251a162
generated by cgit v1.1 at 2025-02-23 00:31:38 +0000