index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
hw
Age
Commit message (
Expand
)
Author
Files
Lines
2019-09-20
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-reques...
Peter Maydell
1
-2
/
+2
2019-09-19
Merge remote-tracking branch 'remotes/kraxel/tags/ati-20190919-pull-request' ...
Peter Maydell
4
-35
/
+60
2019-09-19
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' int...
Peter Maydell
5
-7
/
+12
2019-09-19
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-sf1-v3...
Peter Maydell
15
-280
/
+749
2019-09-19
vfio: fix a typo
Chen Zhang
1
-2
/
+2
2019-09-19
ati: use vga_read_byte in ati_cursor_define
Gerd Hoffmann
1
-9
/
+10
2019-09-19
vga: move access helpers to separate include file
Gerd Hoffmann
3
-26
/
+50
2019-09-18
trace: Remove trailing newline in events
Philippe Mathieu-Daudé
3
-7
/
+7
2019-09-18
loader: Trace loaded images
Alexey Kardashevskiy
2
-0
/
+5
2019-09-17
riscv: sifive_u: Update model and compatible strings in device tree
Bin Meng
1
-2
/
+3
2019-09-17
riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
Bin Meng
1
-23
/
+1
2019-09-17
riscv: sifive_u: Fix broken GEM support
Bin Meng
2
-4
/
+21
2019-09-17
riscv: sifive_u: Instantiate OTP memory with a serial number
Bin Meng
1
-0
/
+9
2019-09-17
riscv: sifive: Implement a model for SiFive FU540 OTP
Bin Meng
2
-0
/
+192
2019-09-17
riscv: sifive_u: Change UART node name in device tree
Bin Meng
1
-1
/
+1
2019-09-17
riscv: sifive_u: Update UART base addresses and IRQs
Bin Meng
1
-2
/
+2
2019-09-17
riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
Bin Meng
1
-3
/
+4
2019-09-17
riscv: sifive_u: Add PRCI block to the SoC
Bin Meng
1
-1
/
+23
2019-09-17
riscv: sifive_u: Generate hfclk and rtcclk nodes
Bin Meng
1
-0
/
+23
2019-09-17
riscv: sifive: Implement PRCI model for FU540
Bin Meng
2
-0
/
+170
2019-09-17
riscv: sifive_u: Update PLIC hart topology configuration string
Bin Meng
1
-3
/
+4
2019-09-17
riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
Bin Meng
1
-25
/
+67
2019-09-17
riscv: sifive_u: Set the minimum number of cpus to 2
Bin Meng
1
-1
/
+4
2019-09-17
riscv: hart: Add a "hartid-base" property to RISC-V hart array
Bin Meng
1
-1
/
+2
2019-09-17
riscv: hart: Extract hart realize to a separate routine
Bin Meng
1
-13
/
+20
2019-09-17
riscv: sifive_e: Drop sifive_mmio_emulate()
Bin Meng
2
-15
/
+9
2019-09-17
riscv: sifive_e: prci: Update the PRCI register block size
Bin Meng
1
-1
/
+1
2019-09-17
riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
Bin Meng
1
-1
/
+1
2019-09-17
riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
Bin Meng
3
-43
/
+42
2019-09-17
riscv: sifive_u: Remove the unnecessary include of prci header
Bin Meng
1
-1
/
+0
2019-09-17
riscv: hw: Remove the unnecessary include of target/riscv/cpu.h
Bin Meng
3
-3
/
+0
2019-09-17
riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead
Bin Meng
3
-9
/
+13
2019-09-17
riscv: hw: Change create_fdt() to return void
Bin Meng
2
-14
/
+8
2019-09-17
riscv: hw: Remove not needed PLIC properties in device tree
Bin Meng
2
-4
/
+0
2019-09-17
riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
Bin Meng
2
-21
/
+21
2019-09-17
riscv: hw: Remove superfluous "linux, phandle" property
Bin Meng
3
-8
/
+0
2019-09-17
riscv: hw: Remove duplicated "hw/hw.h" inclusion
Bin Meng
2
-2
/
+0
2019-09-17
riscv: sifive_test: Add reset functionality
Bin Meng
1
-0
/
+4
2019-09-17
riscv: Resolve full path of the given bios image
Bin Meng
1
-3
/
+3
2019-09-17
riscv: Add a helper routine for finding firmware
Bin Meng
1
-7
/
+15
2019-09-17
riscv: plic: Remove unused interrupt functions
Alistair Francis
1
-12
/
+0
2019-09-17
riscv: sifive_u: Fix clock-names property for ethernet node
Guenter Roeck
1
-1
/
+1
2019-09-17
riscv: sivive_u: Add dummy serial clock and aliases entry for uart
Guenter Roeck
1
-2
/
+17
2019-09-17
riscv: sifive_u: Add support for loading initrd
Guenter Roeck
1
-3
/
+17
2019-09-17
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
Peter Maydell
5
-30
/
+393
2019-09-17
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell
8
-197
/
+257
2019-09-16
virtio-mmio: implement modern (v2) personality (virtio-1)
Sergio Lopez
1
-23
/
+319
2019-09-16
hw/i386/pc: Extract the x86 generic fw_cfg code
Philippe Mathieu-Daudé
3
-131
/
+145
2019-09-16
hw/i386/pc: Rename pc_build_feature_control() as generic fw_cfg_build_*
Philippe Mathieu-Daudé
1
-3
/
+3
2019-09-16
hw/i386/pc: Let pc_build_feature_control() take a MachineState argument
Philippe Mathieu-Daudé
1
-3
/
+2
[next]