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2018-09-25Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20180925' into ↵Peter Maydell1-0/+3
staging HMP pull 2018-09-25 # gpg: Signature made Tue 25 Sep 2018 15:11:09 BST # gpg: using RSA key 0516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert/tags/pull-hmp-20180925: qmp, hmp: add PCI subsystem id and vendor id to PCI info hmp: fix migrate status timer leak monitor: print message when using 'help' with an unknown command Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25aspeed/smc: fix some alignment issuesCédric Le Goater1-4/+4
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180921161939.822-6-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/arm/aspeed: Add an Aspeed machine classCédric Le Goater1-142/+70
The code looks better, it removes duplicated lines and it will ease the introduction of common properties for the Aspeed machines. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180921161939.822-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/arm/aspeed: change the FMC flash model of the AST2500 evbCédric Le Goater1-1/+1
The AST2500 evb is shipped with a W25Q256 which has a non volatile bit to make the chip operate in 4 Byte address mode at power up. This should be an interesting feature to model as it will exercise a bit more the SMC controllers and MMIO execution at boot time. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180921161939.822-3-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25aspeed/timer: fix compile breakage with clang 3.4.2Cédric Le Goater1-1/+0
In file included from /home/thuth/devel/qemu/hw/timer/aspeed_timer.c:16: /home/thuth/devel/qemu/include/hw/misc/aspeed_scu.h:37:3: error: redefinition of typedef 'AspeedSCUState' is a C11 feature [-Werror,-Wtypedef-redefinition] } AspeedSCUState; ^ /home/thuth/devel/qemu/include/hw/timer/aspeed_timer.h:27:31: note: previous definition is here typedef struct AspeedSCUState AspeedSCUState; Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180921161939.822-2-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statementsPeter Maydell1-0/+2
Add 'break' statements missing from a switch in the APB dual-timer write function. Spotted by Coverity as CID 1395626 and 1395633. Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180924123122.14549-1-peter.maydell@linaro.org
2018-09-25hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/writePeter Maydell2-67/+2
The only difference between our implementation of the pcnet ioport accessors and the mmio accessors is that the former check BCR_DWIO to see what access widths are permitted for addresses in the aprom range (0x0..0xf). In fact our failure to do this in the mmio accessors is a bug (one which was fixed for the ioport accessors in commit 7ba79741970 in 2011). The data sheet for the Am79C970A does not describe the DWIO bit as only applying for I/O space mapped I/O resources and not memory mapped I/O resources, and our MMIO accessors already honour DWIO for accesses in the 0x10..0x1f range (since the pcnet_ioport_{read,write}{w,l} functions check it). The data sheet for the later but compatible Am79C976 is clearer: it states specifically "DWIO mode applies to both I/O- and memory-mapped acceses." This seems to be reasonable evidence in favour of interpretating the Am79C970A spec as being the same. (NB: Linux's pcnet driver only supports I/O accesses, so the MMIO access part of this device is probably untested anyway.) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/net/pcnet-pci: Convert away from old_mmio accessorsPeter Maydell2-84/+57
Convert the pcnet-pci device away from using the old_mmio MemoryRegionOps accessor functions. This commit is a no-behaviour-change API conversion. (Since PCNET_PNPMMIO_SIZE is 0x20, the old "addr & 0x10" check and the new "addr < 0x10" check are exact opposites; the new code is phrased to be parallel with the pcnet_io_read/write functions.) I have left a TODO comment marker because the similarity between the MMIO and IO accessor behaviour is suspicious and they could be combined, but this will be left to a different patch. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/intc/arm_gic: Drop GIC_BASE_IRQ macroPeter Maydell3-20/+14
The GIC_BASE_IRQ macro is a leftover from when we shared code between the GICv2 and the v7M NVIC. Since the NVIC is now split off, GIC_BASE_IRQ is always 0, and we can just delete it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180824161819.11085-1-peter.maydell@linaro.org
2018-09-25hw/arm/smmuv3: fix eventq recording and IRQ triggerringEric Auger2-14/+14
The event queue management is broken today. Event records are not properly written as EVT_SET_* macro was not updating the actual event record. Also the event queue interrupt is not correctly triggered. Fixes: bb981004eaf4 ("hw/arm/smmuv3: Event queue recording helper") Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 20180921070138.10114-3-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25qmp, hmp: add PCI subsystem id and vendor id to PCI infoDenis V. Lunev1-0/+3
This is a long story. Red Hat has relicensed Windows KVM device drivers in 2018 and there was an agreement that to avoid WHQL driver conflict software manufacturers should set proper PCI subsystem vendor ID in their distributions. Thus PCI subsystem vendor id becomes actively used. The problem is that this field is applied by us via hardware compats. Thus technically it could be lost. This patch adds PCI susbsystem id and vendor id to exportable parameters for validation. Signed-off-by: Denis V. Lunev <den@openvz.org> CC: "Dr. David Alan Gilbert" <dgilbert@redhat.com> CC: Eric Blake <eblake@redhat.com> CC: Markus Armbruster <armbru@redhat.com> Message-Id: <20180918095852.28422-1-den@openvz.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-09-25hw/arm/smmu-common: Fix the name of the iommu memory regionsEric Auger1-3/+3
At the point smmu_find_add_as() gets called, the bus number might not be computed. Let's change the name of IOMMU memory region and just use the devfn and an incrementing index. The name only is used for debug. Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 20180921070138.10114-2-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: changed 'uint' to 'unsigned int'] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25aspeed/i2c: Fix receive done interrupt handlingGuenter Roeck1-1/+9
The AST2500 datasheet says: I2CD10 Interrupt Status Register bit 2 Receive Done Interrupt status S/W needs to clear this status bit to allow next data receiving The Rx interrupt done interrupt status bit needs to be cleared explicitly before the next byte can be received, and must therefore not be auto-cleared. Also, receiving the next byte must be delayed until the bit has been cleared. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180914063506.20815-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25aspeed/i2c: Handle receive command in separate functionGuenter Roeck1-16/+21
Receive command handling may have to be deferred if a previous receive done interrupt was not yet acknowledged. Move receive command handling into a separate function to prepare for the necessary changes. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180914063506.20815-3-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25aspeed/i2c: interrupts should be cleared by software onlyCédric Le Goater1-4/+12
aspeed i2c interrupts should be cleared by software only, and the bus interrupt should be lowered when all interrupts have been cleared. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180914063506.20815-2-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: drop TODO comment describing an issue which is fixed later in the patch series, and clean up commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25arm: Add BBC micro:bit machineJoel Stanley2-1/+68
This adds the base for a machine model of the BBC micro:bit: https://en.wikipedia.org/wiki/Micro_Bit This is a system with a nRF51 SoC containing the main processor, with various peripherals on board. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20180831220920.27113-4-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25arm: Add Nordic Semiconductor nRF51 SoCJoel Stanley2-0/+134
The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at this stage. Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20180831220920.27113-3-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: wrapped a few long lines] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodesShannon Zhao1-4/+6
Like commit 16b4226(hw/acpi-build: Add a check for memory-less NUMA node ), it also needs to check memory length for NUMA nodes on ARM. Signed-off-by: Shannon Zhao <shannon.zhaosl@gmail.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 20180911112643.19296-1-shenglong.zsl@alibaba-inc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/arm/exynos4210: fix Exynos4210 UART supportBartlomiej Zolnierkiewicz1-4/+4
commit 97274d0c05d4 ("hw/char/exynos4210_uart.c: Remove unneeded handling of NULL chardev") broke Exynos4210 support as it removed NULL 'Chardev *chr' handling from exynos4210_uart_create() and currently exynos4210_init() always passes NULL as 'Chardev *chr' argument to exynos4210_uart_create() calls. Fix it by adding missing serial_hd() calls to exynos4210_init(). Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 9310418.Wg32kryeWE@amdc3058 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180925' ↵Peter Maydell10-39/+89
into staging ppc patch queue 2018-09-25 Here are the accumulated ppc target patches for the last several weeks. Highlights are: * A number of 40p / PReP cleanups * Preliminary irq rework on the pseries machine towards the new XIVE interrupt controller There are a few patches which make small changes to generic device and arm code as prerequisites to the 40p interrupt routing cleanup. They have acks from the relevant maintainers. # gpg: Signature made Tue 25 Sep 2018 08:00:06 BST # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-3.1-20180925: 40p: add fixed IRQ routing for LSI SCSI device lsi53c895a: add optional external IRQ via qdev scsi: remove unused lsi53c895a_create() and lsi53c810_create() functions scsi: move lsi53c8xx_create() callers to lsi53c8xx_handle_legacy_cmdline() scsi: add lsi53c8xx_handle_legacy_cmdline() function sm501: Adjust endianness of pixel value in rectangle fill spapr_pci: add an extra 'nr_msis' argument to spapr_populate_pci_dt spapr: increase the size of the IRQ number space spapr: introduce a spapr_irq class 'nr_msis' attribute 40p: use OR gate to wire up raven PCI interrupts raven: some minor IRQ-related tidy-ups hw/ppc: on 40p machine, change default firmware to OpenBIOS target/ppc/cpu-models: Re-group the 970 CPUs together again Record history of ppcemb target in common.json Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-09-24' ↵Peter Maydell8-30/+18
into staging Error reporting & miscellaneous patches for 2018-09-24 # gpg: Signature made Mon 24 Sep 2018 16:16:50 BST # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-error-2018-09-24: MAINTAINERS: Fix F: patterns that don't match anything Drop "qemu:" prefix from error_report() arguments qemu-error: make use of {error, warn}_report_once_cond qemu-error: add {error, warn}_report_once_cond Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25Merge remote-tracking branch ↵Peter Maydell2-0/+70
'remotes/mcayland/tags/qemu-sparc.for-upstream-20180914' into staging qemu-sparc.for-upstream queue # gpg: Signature made Fri 14 Sep 2018 09:19:56 BST # gpg: using RSA key 5BC2C56FAE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc.for-upstream-20180914: sun4u: implement custom FWPathProvider sabre: generate correct fw path for sabre PCI host bridge Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-2540p: add fixed IRQ routing for LSI SCSI deviceMark Cave-Ayland1-5/+6
Whilst the PReP specification describes how all PCI IRQs are routed via IRQ 15 on the interrupt controller, the real 40p machine has a routing quirk in that the LSI SCSI device is routed directly to IRQ 13. Enable the external IRQ for the LSI SCSI device by wiring up the IRQ with qdev to the relevant interrupt controller gpio. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-25lsi53c895a: add optional external IRQ via qdevMark Cave-Ayland1-2/+14
On some early machines the on-board PCI devices IRQs are wired directly to the interrupt controller instead of via the PCI host bridge. Add an optional external IRQ that if wired up via qdev will replace the in-built PCI IRQ. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-25scsi: remove unused lsi53c895a_create() and lsi53c810_create() functionsMark Cave-Ayland1-14/+0
Now that these functions are no longer required they can be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-25scsi: move lsi53c8xx_create() callers to lsi53c8xx_handle_legacy_cmdline()Mark Cave-Ayland4-4/+10
As part of commits a64aa5785d "hw: Deprecate -drive if=scsi with non-onboard HBAs" and b891538e81 "hw/ppc/prep: Fix implicit creation of "-drive if=scsi" devices" the lsi53c895a_create() and lsi53c810_create() functions were added to wrap pci_create_simple() and scsi_bus_legacy_handle_cmdline(). Unfortunately this prevents us from changing qdev properties on the device and/or changing the PCI configuration. By switching over to using the new lsi53c8xx_handle_legacy_cmdline() function then the caller can now configure and realize the LSI SCSI device exactly as required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> [arm parts] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-25scsi: add lsi53c8xx_handle_legacy_cmdline() functionMark Cave-Ayland1-0/+7
This is the function that will soon be used to replace lsi53c895a_create() and lsi53c810_create(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-25sm501: Adjust endianness of pixel value in rectangle fillMarcus Comstedt1-0/+3
The value from twoD_foreground (which is in host endian format) must be converted to the endianness of the framebuffer (currently always little endian) before it can be used to perform the fill operation. Signed-off-by: Marcus Comstedt <marcus@mc.pp.se> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-25spapr_pci: add an extra 'nr_msis' argument to spapr_populate_pci_dtCédric Le Goater2-7/+4
So that we don't have to call qdev_get_machine() to get the machine class and the sPAPRIrq backend holding the number of MSIs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-25spapr: increase the size of the IRQ number spaceCédric Le Goater2-1/+15
The new layout using static IRQ number does not leave much space to the dynamic MSI range, only 0x100 IRQ numbers. Increase the total number of IRQS for newer machines and introduce a legacy XICS backend for pre-3.1 machines to maintain compatibility. For the old backend, provide a 'nr_msis' value covering the full IRQ number space as it does not use the bitmap allocator to allocate MSI interrupt numbers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-25spapr: introduce a spapr_irq class 'nr_msis' attributeCédric Le Goater2-4/+10
The number of MSI interrupts a sPAPR machine can allocate is in direct relation with the number of interrupts of the sPAPRIrq backend. Define statically this value at the sPAPRIrq class level and use it for the "ibm,pe-total-#msi" property of the sPAPR PHB. According to the PAPR specs, "ibm,pe-total-#msi" defines the maximum number of MSIs that are available to the PE. We choose to advertise the maximum number of MSIs that are available to the machine for simplicity of the model and to avoid segmenting the MSI interrupt pool which can be easily shared. If the pool limit is reached, it can be extended dynamically. Finally, remove XICS_IRQS_SPAPR which is now unused. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-2540p: use OR gate to wire up raven PCI interruptsMark Cave-Ayland2-5/+24
According to the PReP specification section 6.1.6 "System Interrupt Assignments", all PCI interrupts are routed via IRQ 15. Instead of mapping each PCI IRQ separately, we introduce an OR gate within the raven PCI host bridge and then wire the single output of the OR gate to the interrupt controller. Note that whilst the (now deprecated) PReP machine still exists we still need to preserve the old IRQ routing. This is done by adding a new "is-legacy-prep" property to the raven PCI host bridge which is set to true for the PReP machine. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-25raven: some minor IRQ-related tidy-upsMark Cave-Ayland1-6/+5
This really lays the groundwork for the upcoming patches: it renames the irqs PREPPCIState struct member to pci_irqs (as soon there will be a distinction) and then changes the raven IRQ opaque to use PREPPCIState instead of just irqs array. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-25hw/ppc: on 40p machine, change default firmware to OpenBIOSHervé Poussineau1-1/+1
OpenBIOS gained 40p support in 5b20e4cacecb62fb2bdc6867c11d44cddd77c4ff Use it, instead of relying on an unmaintained and very limited firmware. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-09-24Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell7-107/+90
pci, pc, virtio: fixes, features pci resource capability + misc fixes everywhere. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Fri 07 Sep 2018 22:50:38 BST # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: tests: update acpi expected files vhost: fix invalid downcast pc: make sure that guest isn't able to unplug the first cpu hw/pci: add PCI resource reserve capability to legacy PCI bridge hw/pci: factor PCI reserve resources to a separate structure virtio: update MemoryRegionCaches when guest negotiates features pc: acpi: revert back to 1 SRAT entry for hotpluggable area Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-24Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180907' ↵Peter Maydell15-80/+194
into staging ppc patch queue 2018-09-07 Here's another pull request for qemu-3.1. No real theme here, just an assortment of various fixes. Probably the most notable thing is the removal of the ppcemb target which has been deprecated for some time now. # gpg: Signature made Fri 07 Sep 2018 08:30:02 BST # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-3.1-20180907: target-ppc: Extend HWCAP2 bits for ISA 3.0 target/ppc/kvm: set vcpu as online/offline Fix a deadlock case in the CPU hotplug flow spapr: Correct reference count on spapr-cpu-core mac_newworld: implement custom FWPathProvider uninorth: add ofw-addr property to allow correct fw path generation mac_oldworld: implement custom FWPathProvider grackle: set device fw_name and address for correct fw path generation macio: add addr property to macio IDE object macio: add macio bus to help with fw path generation macio: move MACIOIDEState type declarations to macio.h spapr_pci: fix potential NULL pointer dereference spapr: fix leak of rev array ppc: Remove deprecated ppcemb target Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-24Merge remote-tracking branch ↵Peter Maydell3-29/+24
'remotes/alistair/tags/pull-riscv-pullreq-20180905' into staging A misc collection of RISC-V related patches for 3.1. # gpg: Signature made Wed 05 Sep 2018 23:06:55 BST # gpg: using RSA key 21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-pullreq-20180905: riscv: remove define cpu_init() hw/riscv/spike: Set the soc device tree node as a simple-bus hw/riscv/virtio: Set the soc device tree node as a simple-bus target/riscv: call gen_goto_tb on DISAS_TOO_MANY target/riscv: optimize indirect branches target/riscv: optimize cross-page direct jumps in softmmu RISC-V: Simplify riscv_cpu_local_irqs_pending RISC-V: Use atomic_cmpxchg to update PLIC bitmaps RISC-V: Improve page table walker spec compliance RISC-V: Update address bits to support sv39 and sv48 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-24Merge remote-tracking branch 'remotes/kraxel/tags/vga-20180903-pull-request' ↵Peter Maydell10-60/+48
into staging vga: virtio reset fix, virtio iommu support. # gpg: Signature made Mon 03 Sep 2018 07:57:32 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20180903-pull-request: virtio-gpu: add iommu support virtio-gpu: pass down VirtIOGPU pointer to a bunch of functions use dpy_gfx_update_full Revert "virtio-gpu: fix crashes upon warm reboot with vga mode" virtio-vga: fix reset Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-24Drop "qemu:" prefix from error_report() argumentsMao Zhongyi7-15/+15
error_report and friends already add a "qemu-system-xxx" prefix to the string, so a "qemu:" prefix is redundant in the string. Just drop it. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1537495530-580-1-git-send-email-maozhongyi@cmss.chinamobile.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-09-24qemu-error: add {error, warn}_report_once_condCornelia Huck1-15/+3
Add two functions to print an error/warning report once depending on a passed-in condition variable and flip it if printed. This is useful if you want to print a message not once-globally, but e.g. once-per-device. Inspired by warn_once() in hw/vfio/ccw.c, which has been replaced with warn_report_once_cond(). Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20180830145902.27376-2-cohuck@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Function comments reworded] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-09-24Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180829' into stagingPeter Maydell13-669/+887
- various fixes and improvements in the tcg code - split off the individual virtio-ccw devices into separate files # gpg: Signature made Wed 29 Aug 2018 10:38:03 BST # gpg: using RSA key DECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # gpg: aka "Cornelia Huck <cohuck@kernel.org>" # gpg: aka "Cornelia Huck <cohuck@redhat.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20180829: target/s390x: use regular spaces in translate.c hw/s390x: Move virtio-ccw-blk code to a separate file hw/s390x: Move virtio-ccw-net code to a separate file hw/s390x: Move virtio-ccw-input code to a separate file hw/s390x: Move virtio-ccw-gpu code to a separate file hw/s390x: Move vhost-vsock-ccw code to a separate file hw/s390x: Move virtio-ccw-crypto code to a separate file hw/s390x: Move virtio-ccw-9p code to a separate file hw/s390x: Move virtio-ccw-rng code to a separate file hw/s390x: Move virtio-ccw-scsi code to a separate file hw/s390x: Move virtio-ccw-balloon code to a separate file hw/s390x: Move virtio-ccw-serial code to a separate file hw/s390x/virtio-ccw: Consolidate calls to virtio_ccw_unrealize() target/s390x: fix PACK reading 1 byte less and writing 1 byte more target/s390x: add EX support for TRT and TRTR target/s390x: fix IPM polluting irrelevant bits target/s390x: fix CSST decoding and runtime alignment check target/s390x: add BAL and BALR instructions tests/tcg: add a simple s390x test Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-14sun4u: implement custom FWPathProviderMark Cave-Ayland1-0/+58
This enables the correct generation of bootdevice fw paths for in-built IDE and virtio-pci-blk devices suitable for OpenBIOS. Note we also set the MachineClass ignore_boot_device_suffixes property to true to allow the correct customisation of the disk node names as required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2018-09-14sabre: generate correct fw path for sabre PCI host bridgeMark Cave-Ayland1-0/+12
Set the fw_name property to "pci" and also set an explicit OFW address using the value of the special_base property. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2018-09-07vhost: fix invalid downcastYury Kotov1-3/+1
virtio_queue_get_desc_addr returns 64-bit hwaddr while int is usually 32-bit. If returned hwaddr is not equal to 0 but least-significant 32 bits are equal to 0 then this code will not actually stop running queue. Signed-off-by: Yury Kotov <yury-kotov@yandex-team.ru> Acked-by: Jia He <hejianet@gmail.com> Cc: qemu-stable@nongnu.org Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-09-07pc: make sure that guest isn't able to unplug the first cpuIgor Mammedov1-4/+6
The first cpu unplug wasn't ever supported and corresponding monitor/qmp commands refuse to unplug it. However guest is able to issue eject request either using following command: # echo 1 >/sys/devices/system/cpu/cpu0/firmware_node/eject or directly writing to cpu hotplug registers, which makes qemu crash with SIGSEGV following back trace: kvm_flush_coalesced_mmio_buffer () while (ring->first != ring->last) ... qemu_flush_coalesced_mmio_buffer prepare_mmio_access flatview_read_continue flatview_read address_space_read_full address_space_rw kvm_cpu_exec(cpu!0) qemu_kvm_cpu_thread_fn the reason for which is that ring == KVMState::coalesced_mmio_ring happens to be a part of 1st CPU that was uplugged by guest. Fix it by forbidding 1st cpu unplug from guest side and in addition remove CPU0._EJ0 ACPI method to make clear that unplug of the first CPU is not supported. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-09-07hw/pci: add PCI resource reserve capability to legacy PCI bridgeJing Liu1-0/+24
Add hint to firmware (e.g. SeaBIOS) to reserve addtional BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the resource reserve capability deleting in pci_bridge_dev_exitfn. Signed-off-by: Jing Liu <jing2.liu@linux.intel.com> Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-09-07hw/pci: factor PCI reserve resources to a separate structureJing Liu2-37/+34
Factor "bus_reserve", "io_reserve", "mem_reserve", "pref32_reserve" and "pref64_reserve" fields of the "GenPCIERootPort" structure out to "PCIResReserve" structure, so that other PCI bridges can reuse it to add resource reserve capability. Signed-off-by: Jing Liu <jing2.liu@linux.intel.com> Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-09-07virtio: update MemoryRegionCaches when guest negotiates featuresPaolo Bonzini1-2/+13
Because the cache is sized to include the rings and the event indices, negotiating the VIRTIO_RING_F_EVENT_IDX feature will result in the size of the cache changing. And because MemoryRegionCache accesses are range-checked, if we skip this we end up with an assertion failure. This happens with OpenBSD 6.3. Reported-by: Fam Zheng <famz@redhat.com> Fixes: 97cd965c070152bc626c7507df9fb356bbe1cd81 Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Tested-by: Fam Zheng <famz@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-09-07pc: acpi: revert back to 1 SRAT entry for hotpluggable areaIgor Mammedov1-61/+12
Commit 10efd7e108 "pc: acpi: fix memory hotplug regression by reducing stub SRAT entry size" attemped to fix hotplug regression introduced by 848a1cc1e "hw/acpi-build: build SRAT memory affinity structures for DIMM devices" fixed issue for Windows/3.0+ linux kernels, however it regressed 2.6 based kernels (RHEL6) to the point where guest might crash at boot. Reason is that 2.6 kernel discards SRAT table due too small last entry which down the road leads to crashes. Hack I've tried in 10efd7e108 is also not ACPI spec compliant according to which whole possible RAM should be described in SRAT. Revert 10efd7e108 to fix regression for 2.6 based kernels. With 10efd7e108 reverted, I've also tried splitting SRAT table statically in different ways %/node and %/slot but Windows still fails to online 2nd pc-dimm hot-plugged into node 0 (as described in 10efd7e108) and sometimes even coldplugged pc-dimms where affected with static SRAT partitioning. The only known so far way where Windows stays happy is when we have 1 SRAT entry in the last node covering all hotplug area. Revert 848a1cc1e until we come up with a way to avoid regression on Windows with hotplug area split in several entries. Tested this with 2.6/3.0 based kernels (RHEL6/7) and WS20[08/12/12R2/16]). Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-09-05hw/riscv/spike: Set the soc device tree node as a simple-busAlistair Francis1-1/+1
To allow Linux to enumerate devices on the /soc/ node set it as a "simple-bus". Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.1 at 2024-12-29 10:41:38 +0000