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2018-03-09Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell2-13/+35
staging # gpg: Signature made Fri 09 Mar 2018 13:19:02 GMT # gpg: using RSA key 9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: vl: introduce vm_shutdown() virtio-scsi: fix race between .ioeventfd_stop() and vq handler virtio-blk: fix race between .ioeventfd_stop() and vq handler block: add aio_wait_bh_oneshot() virtio-blk: dataplane: Don't batch notifications if EVENT_IDX is present README: Fix typo 'git-publish' block: Fix qemu crash when using scsi-block Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-09Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-upstream-v8.2' ↵Peter Maydell13-2/+2860
into staging QEMU RISC-V Emulation Support (RV64GC, RV32GC) This release renames the SiFive machines to sifive_e and sifive_u to represent the SiFive Everywhere and SiFive Unleashed platforms. SiFive has configurable soft-core IP, so it is intended that these machines will be extended to enable a variety of SiFive IP blocks. The CPU definition infrastructure has been improved and there are now vendor CPU modules including the SiFiVe E31, E51, U34 and U54 cores. The emulation accuracy for the E series has been improved by disabling the MMU for the E series. S mode has been disabled on cores that only support M mode and U mode. The two Spike machines that support two privileged ISA versions have been coalesced into one file. This series has Signed-off-by from the core contributors. *** Known Issues *** * Disassembler has some checkpatch warnings for the sake of code brevity * scripts/qemu-binfmt-conf.sh has checkpatch warnings due to line length * PMP (Physical Memory Protection) is as-of-yet unused and needs testing *** Changelog *** v8.2 * Rebase v8.1 * Fix missed case of renaming spike_v1.9 to spike_v1.9.1 v8 * Added linux-user/riscv/target_elf.h during rebase * Make resetvec configurable and clear mpp and mie on reset * Use SiFive E31, E51, U34 and U54 cores in SiFive machines * Define SiFive E31, E51, U34 and U54 cores * Refactor CPU core definition in preparation for vendor cores * Prevent S or U mode unless S or U extensions are present * SiFive E Series cores have no MMU * SiFive E Series cores have U mode * Make privileged ISA v1.10 implicit in CPU types * Remove DRAM_BASE and EXT_IO_BASE as they vary by machine * Correctly handle mtvec and stvec alignment with respect to RVC * Print more machine mode state in riscv_cpu_dump_state * Make riscv_isa_string use compact extension order method * Fix bug introduced in v6 RISCV_CPU_TYPE_NAME macro change * Parameterize spike v1.9.1 config string * Coalesce spike_v1.9.1 and spike_v1.10 machines * Rename sifive_e300 to sifive_e, and sifive_u500 to sifive_u v7 * Make spike_v1.10 the default machine * Rename spike_v1.9 to spike_v1.9.1 to match privileged spec version * Remove empty target/riscv/trace-events file * Monitor ROM 32-bit reset code needs to be target endian * Add TARGET_TIOCGPTPEER to linux-user/riscv/termbits.h * Add -initrd support to the virt board * Fix naming in spike machine interface header * Update copyright notice on RISC-V Spike machines * Update copyright notice on RISC-V HTIF Console device * Change CPU Core and translator to GPLv2+ * Change RISC-V Disassembler to GPLv2+ * Change SiFive Test Finisher to GPLv2+ * Change SiFive CLINT to GPLv2+ * Change SiFive PRCI to GPLv2+ * Change SiFive PLIC to GPLv2+ * Change RISC-V spike machines to GPLv2+ * Change RISC-V virt machine to GPLv2+ * Change SiFive E300 machine to GPLv2+ * Change SiFive U500 machine to GPLv2+ * Change RISC-V Hart Array to GPLv2+ * Change RISC-V HTIF device to GPLv2+ * Change SiFiveUART device to GPLv2+ v6 * Drop IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax * Remove some unnecessary commented debug statements * Change RISCV_CPU_TYPE_NAME to use riscv-cpu suffix * Define all CPU variants for linux-user * qemu_log calls require trailing \n * Replace PLIC printfs with qemu_log * Tear out unused HTIF code and eliminate shouting debug messages * Fix illegal instruction when sfence.vma is passed (rs2) arguments * Make updates to PTE accessed and dirty bits atomic * Only require atomic PTE updates on MTTCG enabled guests * Page fault if accessed or dirty bits can't be updated * Fix get_physical_address PTE reads and writes on riscv32 * Remove erroneous comments from the PLIC * Default enable MTTCG * Make WFI less conservative * Unify local interrupt handling * Expunge HTIF interrupts * Always access mstatus.mip under a lock * Don't implement rdtime/rdtimeh in system mode (bbl emulates them) * Implement insreth/cycleh for rv32 and always enable user-mode counters * Add GDB stub support for reading and writing CSRs * Rename ENABLE_CHARDEV #ifdef from HTIF code * Replace bad HTIF ELF code with load_elf symbol callback * Convert chained if else fault handlers to switch statements * Use RISCV exception codes for linux-user page faults v5 * Implement NaN-boxing for flw, set high order bits to 1 * Use float_muladd_negate_* flags to floatXX_muladd * Use IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax * Fix TARGET_NR_syscalls * Update linux-user/riscv/syscall_nr.h * Fix FENCE.I, needs to terminate translation block * Adjust unusual convention for interruptno >= 0 v4 * Add @riscv: since 2.12 to CpuInfoArch * Remove misleading little-endian comment from load_kernel * Rename cpu-model property to cpu-type * Drop some unnecessary inline function attributes * Don't allow GDB to set value of x0 register * Remove unnecessary empty property lists * Add Test Finisher device to implement poweroff in virt machine * Implement priv ISA v1.10 trap and sret/mret xPIE/xIE behavior * Store fflags data in fp_status * Purge runtime users of helper_raise_exception * Fix validate_csr * Tidy gen_jalr * Tidy immediate shifts * Add gen_exception_inst_addr_mis * Add gen_exception_debug * Add gen_exception_illegal * Tidy helper_fclass_* * Split rounding mode setting to a new function * Enforce MSTATUS_FS via TB flags * Implement acquire/release barrier semantics * Use atomic operations as required * Fix FENCE and FENCE_I * Remove commented code from spike machines * PAGE_WRITE permissions can be set on loads if page is already dirty * The result of format conversion on an NaN must be a quiet NaN * Add missing process_queued_cpu_work to riscv linux-user * Remove float(32|64)_classify from cpu.h * Removed nonsensical unions aliasing the same type * Use uintN_t instead of uintN_fast_t in fpu_helper.c * Use macros for FPU exception values in softfloat_flags_to_riscv * Move code to set round mode into set_fp_round_mode function * Convert set_fp_exceptions from a macro to an inline function * Convert round mode helper into an inline function * Make fpu_helper ieee_rm array static const * Include cpu_mmu_index in cpu_get_tb_cpu_state flags * Eliminate MPRV influence on mmu_index * Remove unrecoverable do_unassigned_access function * Only update PTE accessed and dirty bits if necessary * Remove unnecessary tlb_flush in set_mode as mode is in mmu_idx * Remove buggy support for misa writes. misa writes are optional and are not implemented in any known hardware * Always set PTE read or execute permissions during page walk * Reorder helper function declarations to match order in helper.c * Remove redundant variable declaration in get_physical_address * Remove duplicated code from get_physical_address * Use mmu_idx instead of mem_idx in riscv_cpu_get_phys_page_debug v3 * Fix indentation in PMP and HTIF debug macros * Fix disassembler checkpatch open brace '{' on next line errors * Fix trailing statements on next line in decode_inst_decompress * NOTE: the other checkpatch issues have been reviewed previously v2 * Remove redundant NULL terminators from disassembler register arrays * Change disassembler register name arrays to const * Refine disassembler internal function names * Update dates in disassembler copyright message * Remove #ifdef CONFIG_USER_ONLY version of cpu_has_work * Use ULL suffix on 64-bit constants * Move riscv_cpu_mmu_index from cpu.h to helper.c * Move riscv_cpu_hw_interrupts_pending from cpu.h to helper.c * Remove redundant TARGET_HAS_ICE from cpu.h * Use qemu_irq instead of void* for irq definition in cpu.h * Remove duplicate typedef from struct CPURISCVState * Remove redundant g_strdup from cpu_register * Remove redundant tlb_flush from riscv_cpu_reset * Remove redundant mode calculation from get_physical_address * Remove redundant debug mode printf and dcsr comment * Remove redundant clearing of MSB for bare physical addresses * Use g_assert_not_reached for invalid mode in get_physical_address * Use g_assert_not_reached for unreachable checks in get_physical_address * Use g_assert_not_reached for unreachable type in raise_mmu_exception * Return exception instead of aborting for misaligned fetches * Move exception defines from cpu.h to cpu_bits.h * Remove redundant breakpoint control definitions from cpu_bits.h * Implement riscv_cpu_unassigned_access exception handling * Log and raise exceptions for unimplemented CSRs * Match Spike HTIF exit behavior - don’t print TEST-PASSED * Make frm,fflags,fcsr writes trap when mstatus.FS is clear * Use g_assert_not_reached for unreachable invalid mode * Make hret,uret,dret generate illegal instructions * Move riscv_cpu_dump_state and int/fpr regnames to cpu.c * Lift interrupt flag and mask into constants in cpu_bits.h * Change trap debugging to use qemu_log_mask LOG_TRACE * Change CSR debugging to use qemu_log_mask LOG_TRACE * Change PMP debugging to use qemu_log_mask LOG_TRACE * Remove commented code from pmp.c * Change CpuInfoRISCV qapi schema docs to Since 2.12 * Change RV feature macro to use target_ulong cast * Remove riscv_feature and instead use misa extension flags * Make riscv_flush_icache_syscall a no-op * Undo checkpatch whitespace fixes in unrelated linux-user code * Remove redudant constants and tidy up cpu_bits.h * Make helper_fence_i a no-op * Move include "exec/cpu-all" to end of cpu.h * Rename set_privilege to riscv_set_mode * Move redundant forward declaration for cpu_riscv_translate_address * Remove TCGV_UNUSED from riscv_translate_init * Add comment to pmp.c stating the code is untested and currently unused * Use ctz to simplify decoding of PMP NAPOT address ranges * Change pmp_is_in_range to use than equal for end addresses * Fix off by one error in pmp_update_rule * Rearrange PMP_DEBUG so that formatting is compile-time checked * Rearrange trap debugging so that formatting is compile-time checked * Rearrange PLIC debugging so that formatting is compile-time checked * Use qemu_log/qemu_log_mask for HTIF logging and debugging * Move exception and interrupt names into cpu.c * Add Palmer Dabbelt as a RISC-V Maintainer * Rebase against current qemu master branch v1 * initial version based on forward port from riscv-qemu repository *** Background *** "RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation." The QEMU RISC-V port has been developed and maintained out-of-tree for several years by Sagar Karandikar and Bastian Koppelmann. The RISC-V Privileged specification has evolved substantially over this period but has recently been solidifying. The RISC-V Base ISA has been frozon for some time and the Privileged ISA, GCC toolchain and Linux ABI are now quite stable. I have recently joined Sagar and Bastian as a RISC-V QEMU Maintainer and hope to support upstreaming the port. There are multiple vendors taping out, preparing to ship, or shipping silicon that implements the RISC-V Privileged ISA Version 1.10. There are also several RISC-V Soft-IP cores implementing Privileged ISA Version 1.10 that run on FPGA such as SiFive's Freedom U500 Platform and the U54‑MC RISC-V Core IP, among many more implementations from a variety of vendors. See https://riscv.org/ for more details. RISC-V support was upstreamed in binutils 2.28 and GCC 7.1 in the first half of 2016. RISC-V support is now available in LLVM top-of-tree and the RISC-V Linux port was accepted into Linux 4.15-rc1 late last year and is available in the Linux 4.15 release. GLIBC 2.27 added support for the RISC-V ISA running on Linux (requires at least binutils-2.30, gcc-7.3.0, and linux-4.15). We believe it is timely to submit the RISC-V QEMU port for upstream review with the goal of incorporating RISC-V support into the upcoming QEMU 2.12 release. The RISC-V QEMU port is still under active development, mostly with respect to device emulation, the addition of Hypervisor support as specified in the RISC-V Draft Privileged ISA Version 1.11, and Vector support once the first draft is finalized later this year. We believe now is the appropriate time for RISC-V QEMU development to be carried out in the main QEMU repository as the code will benefit from more rigorous review. The RISC-V QEMU port currently supports all the ISA extensions that have been finalized and frozen in the Base ISA. Blog post about recent additions to RISC-V QEMU: https://goo.gl/fJ4zgk The RISC-V QEMU wiki: https://github.com/riscv/riscv-qemu/wiki Instructions for building a busybox+dropbear root image, BBL (Berkeley Boot Loader) and linux kernel image for use with the RISC-V QEMU 'virt' machine: https://github.com/michaeljclark/busybear-linux *** Overview *** The RISC-V QEMU port implements the following specifications: * RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 * RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1 * RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 The RISC-V QEMU port supports the following instruction set extensions: * RV32GC with Supervisor-mode and User-mode (RV32IMAFDCSU) * RV64GC with Supervisor-mode and User-mode (RV64IMAFDCSU) The RISC-V QEMU port adds the following targets to QEMU: * riscv32-softmmu * riscv64-softmmu * riscv32-linux-user * riscv64-linux-user The RISC-V QEMU port supports the following hardware: * HTIF Console (Host Target Interface) * SiFive CLINT (Core Local Interruptor) for Timer interrupts and IPIs * SiFive PLIC (Platform Level Interrupt Controller) * SiFive Test (Test Finisher) for exiting simulation * SiFive UART, PRCI, AON, PWM, QSPI support is partially implemented * VirtIO MMIO (GPEX PCI support will be added in a future patch) * Generic 16550A UART emulation using 'hw/char/serial.c' * MTTCG and SMP support (PLIC and CLINT) on the 'virt' machine The RISC-V QEMU full system emulator supports 5 machines: * 'spike_v1.9.1', CLINT, PLIC, HTIF console, config-string, Priv v1.9.1 * 'spike_v1.10', CLINT, PLIC, HTIF console, device-tree, Priv v1.10 * 'sifive_e', CLINT, PLIC, SiFive UART, HiFive1 compat, Priv v1.10 * 'sifive_u', CLINT, PLIC, SiFive UART, device-tree, Priv v1.10 * 'virt', CLINT, PLIC, 16550A UART, VirtIO, device-tree, Priv v1.10 This is a list of RISC-V QEMU Port Contributors: * Alex Suykov * Andreas Schwab * Antony Pavlov * Bastian Koppelmann * Bruce Hoult * Chih-Min Chao * Daire McNamara * Darius Rad * David Abdurachmanov * Hesham Almatary * Ivan Griffin * Jim Wilson * Kito Cheng * Michael Clark * Palmer Dabbelt * Richard Henderson * Sagar Karandikar * Shea Levy * Stefan O'Rear Notes: * contributor email addresses available off-list on request. * checkpatch has been run on all 23 patches. * checkpatch exceptions are noted in patches that have errors. * passes "make check" on full build for all targets * tested riscv-linux-4.6.2 on 'spike_v1.9.1' machine * tested riscv-linux-4.15 on 'spike_v1.10' and 'virt' machines * tested SiFive HiFive1 binaries in 'sifive_e' machine * tested RV64 on 32-bit i386 This patch series includes the following patches: # gpg: Signature made Thu 08 Mar 2018 19:40:20 GMT # gpg: using DSA key 6BF1D7B357EF3E4F # gpg: Good signature from "Michael Clark <michaeljclark@mac.com>" # gpg: aka "Michael Clark <mjc@sifive.com>" # gpg: aka "Michael Clark <michael@metaparadigm.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7C99 930E B17C D8BA 073D 5EFA 6BF1 D7B3 57EF 3E4F * remotes/riscv/tags/riscv-qemu-upstream-v8.2: (23 commits) RISC-V Build Infrastructure SiFive Freedom U Series RISC-V Machine SiFive Freedom E Series RISC-V Machine SiFive RISC-V PRCI Block SiFive RISC-V UART Device RISC-V VirtIO Machine SiFive RISC-V Test Finisher RISC-V Spike Machines SiFive RISC-V PLIC Block SiFive RISC-V CLINT Block RISC-V HART Array RISC-V HTIF Console Add symbol table callback interface to load_elf RISC-V Linux User Emulation RISC-V Physical Memory Protection RISC-V TCG Code Generation RISC-V GDB Stub RISC-V FPU Support RISC-V CPU Helpers RISC-V Disassembler ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-08virtio-scsi: fix race between .ioeventfd_stop() and vq handlerStefan Hajnoczi1-4/+5
If the main loop thread invokes .ioeventfd_stop() just as the vq handler function begins in the IOThread then the handler may lose the race for the AioContext lock. By the time the vq handler is able to acquire the AioContext lock the ioeventfd has already been removed and the handler isn't supposed to run anymore! Use the new aio_wait_bh_oneshot() function to perform ioeventfd removal from within the IOThread. This way no races with the vq handler are possible. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20180307144205.20619-4-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-08virtio-blk: fix race between .ioeventfd_stop() and vq handlerStefan Hajnoczi1-7/+17
If the main loop thread invokes .ioeventfd_stop() just as the vq handler function begins in the IOThread then the handler may lose the race for the AioContext lock. By the time the vq handler is able to acquire the AioContext lock the ioeventfd has already been removed and the handler isn't supposed to run anymore! Use the new aio_wait_bh_oneshot() function to perform ioeventfd removal from within the IOThread. This way no races with the vq handler are possible. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20180307144205.20619-3-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-08s390x/virtio: Convert virtio-ccw from *_exit to *_unrealizeNia Alarie2-18/+18
Signed-off-by: Nia Alarie <nia.alarie@gmail.com> Message-Id: <20180307162958.11232-1-nia.alarie@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-08virtio-blk: dataplane: Don't batch notifications if EVENT_IDX is presentSergio Lopez1-2/+13
Commit 5b2ffbe4d99843fd8305c573a100047a8c962327 ("virtio-blk: dataplane: notify guest as a batch") deferred guest notification to a BH in order batch notifications, with purpose of avoiding flooding the guest with interruptions. This optimization came with a cost. The average latency perceived in the guest is increased by a few microseconds, but also when multiple IO operations finish at the same time, the guest won't be notified until all completions from each operation has been run. On the contrary, virtio-scsi issues the notification at the end of each completion. On the other hand, nowadays we have the EVENT_IDX feature that allows a better coordination between QEMU and the Guest OS to avoid sending unnecessary interruptions. With this change, virtio-blk/dataplane only batches notifications if the EVENT_IDX feature is not present. Some numbers obtained with fio (ioengine=sync, iodepth=1, direct=1): - Test specs: * fio-3.4 (ioengine=sync, iodepth=1, direct=1) * qemu master * virtio-blk with a dedicated iothread (default poll-max-ns) * backend: null_blk nr_devices=1 irqmode=2 completion_nsec=280000 * 8 vCPUs pinned to isolated physical cores * Emulator and iothread also pinned to separate isolated cores * variance between runs < 1% - Not patched * numjobs=1: lat_avg=327.32 irqs=29998 * numjobs=4: lat_avg=337.89 irqs=29073 * numjobs=8: lat_avg=342.98 irqs=28643 - Patched: * numjobs=1: lat_avg=323.92 irqs=30262 * numjobs=4: lat_avg=332.65 irqs=29520 * numjobs=8: lat_avg=335.54 irqs=29323 Signed-off-by: Sergio Lopez <slp@redhat.com> Message-id: 20180307114459.26636-1-slp@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-08s390x/sclp: clean up sclp masksClaudio Imbrenda5-18/+18
Introduce an sccb_mask_t to be used for SCLP event masks instead of just unsigned int or uint32_t. This will allow later to extend the mask with more ease. Signed-off-by: Claudio Imbrenda <imbrenda@linux.vnet.ibm.com> Message-Id: <1519407778-23095-3-git-send-email-imbrenda@linux.vnet.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-08s390x/sclp: proper support of larger send and receive masksClaudio Imbrenda2-14/+75
Until 67915de9f0383ccf4a ("s390x/event-facility: variable-length event masks") we only supported sclp event masks with a size of exactly 4 bytes, even though the architecture allows the guests to set up sclp event masks from 1 to 1021 bytes in length. After that patch, the behaviour was almost compliant, but some issues were still remaining, in particular regarding the handling of selective reads and migration. When setting the sclp event mask, a mask size is also specified. Until now we only considered the size in order to decide which bits to save in the internal state. On the other hand, when a guest performs a selective read, it sends a mask, but it does not specify a size; the implied size is the size of the last mask that has been set. Specifying bits in the mask of selective read that are not available in the internal mask should return an error, and bits past the end of the mask should obviously be ignored. This can only be achieved by keeping track of the lenght of the mask. The mask length is thus now part of the internal state that needs to be migrated. This patch fixes the handling of selective reads, whose size will now match the length of the event mask, as per architecture. While the default behaviour is to be compliant with the architecture, when using older machine models the old broken behaviour is selected (allowing only masks of size exactly 4), in order to be able to migrate toward older versions. Fixes: 67915de9f0383ccf4a ("s390x/event-facility: variable-length event masks") Signed-off-by: Claudio Imbrenda <imbrenda@linux.vnet.ibm.com> Message-Id: <1519407778-23095-2-git-send-email-imbrenda@linux.vnet.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-08vfio-ccw: license text should indicate GPL v2 or laterCornelia Huck1-2/+2
The license text currently specifies "any version" of the GPL. It is unlikely that GPL v1 was ever intended; change this to the standard "or any later version" text. Cc: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Cc: Xiao Feng Ren <renxiaof@linux.vnet.ibm.com> Cc: Pierre Morel <pmorel@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Acked-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-08s390x/sclpconsole: Remove dead code - remove exit handlersNia Alarie3-26/+0
The other event handlers (quiesce and cpu) do not define these handlers, and this one does nothing, so it can be removed. Signed-off-by: Nia Alarie <nia.alarie@gmail.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20180306100721.19419-1-nia.alarie@gmail.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-08numa: we don't implement NUMA for s390xDavid Hildenbrand1-3/+5
Right now it is possible to crash QEMU for s390x by providing e.g. -numa node,nodeid=0,cpus=0-1 Problem is, that numa.c uses mc->cpu_index_to_instance_props as an indicator whether NUMA is supported by a machine type. We don't implement NUMA for s390x ("topology") yet. However we need mc->cpu_index_to_instance_props for query-cpus. So let's fix this case by also checking for mc->get_default_cpu_node_id, which will be needed by machine_set_cpu_numa_node(). qemu-system-s390x: -numa node,nodeid=0,cpus=0-1: NUMA is not supported by this machine-type While at it, make s390_cpu_index_to_props() look like on other architectures. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180227110255.20999-1-david@redhat.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-08hw/s390x: Add the possibility to specify the netboot image on the command lineThomas Huth1-1/+3
The file name of the netboot binary is currently hard-coded to "s390-netboot.img", without a possibility for the user to select an alternative firmware image here. That's unfortunate, especially since the basics are already there: The filename is a property of the s390-ipl device. So we just have to add a check whether the user already provided the property and only set the default if the string is still empty. Now it is possible to select a different firmware image with "-global s390-ipl.netboot_fw=/path/to/s390-netboot.img". Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1519731154-3127-1-git-send-email-thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-08s390/ipl: only print boot menu error if -boot menu=on was specifiedCollin L. Walling1-4/+6
It is possible that certain QEMU configurations may not create an IPLB (such as when -kernel is provided). In this case, a misleading error message will be printed stating that the "boot menu is not supported for this device type". To amend this, only print this message iff boot menu=on was provided on the commandline. Otherwise, return silently. While we're at it, remove trailing periods from error messages. Signed-off-by: Collin L. Walling <walling@linux.vnet.ibm.com> Message-Id: <1519760121-24594-1-git-send-email-walling@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-08hw/s390x/ipl: Bail out if the network bootloader can not be foundThomas Huth1-2/+3
If QEMU fails to load 's390-netboot.img', the guest firmware currently loops forever and just floods the console with "Network boot device detected" messages. The code in ipl.c apparently already tried to stop the VM with vm_stop() in this case, but this is in vain since the run state is later reset due to a call to vm_start() from vl.c again. To avoid the ugly firmware loop, let's simply exit QEMU directly instead since it just does not make sense to continue if the required firmware image can not be loaded. While we're at it, also add the file name of the netboot binary to the error message, so that the user has a better hint about what is missing. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1519725913-24852-1-git-send-email-thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Farhan Ali <alifm@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-08Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into ↵Peter Maydell1-0/+1
staging qemu-sparc update # gpg: Signature made Thu 08 Mar 2018 07:23:01 GMT # gpg: using RSA key 5BC2C56FAE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-signed: sparc: fix leon3 casa instruction when MMU is disabled hw/sparc/sun4m: Fix implicit creation of "-drive if=scsi" devices Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-08Merge remote-tracking branch ↵Peter Maydell6-114/+134
'remotes/stefanberger/tags/pull-tpm-2018-03-07-1' into staging Merge tpm 2018/03/07 # gpg: Signature made Wed 07 Mar 2018 12:42:13 GMT # gpg: using RSA key 75AD65802A0B4211 # gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B818 B9CA DF90 89C2 D5CE C66B 75AD 6580 2A0B 4211 * remotes/stefanberger/tags/pull-tpm-2018-03-07-1: tpm: convert tpm_tis.c to use trace-events tpm: convert tpm_emulator.c to use trace-events tpm: convert tpm_util.c to use trace-events tpm: convert tpm_passthrough.c to use trace-events tpm: convert tpm_crb.c to use trace-events Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-08hw/sparc/sun4m: Fix implicit creation of "-drive if=scsi" devicesThomas Huth1-0/+1
The global hack for creating SCSI devices has recently been removed, but this apparently broke SCSI devices on some boards that were not ready for this change yet. For the sun4m machines you now get: $ sparc-softmmu/qemu-system-sparc -boot d -cdrom x.iso qemu-system-sparc: -cdrom x.iso: machine type does not support if=scsi,bus=0,unit=2 Fix it by calling scsi_bus_legacy_handle_cmdline() after creating the corresponding SCSI controller. Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Fixes: 1454509726719e0933c800fad00d6999752688ea Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2018-03-07multiboot: fprintf(stderr...) -> error_report()Jack Schwartz1-26/+29
Change all fprintf(stderr...) calls in hw/i386/multiboot.c to call error_report() instead, including the mb_debug macro. Remove the "\n" from strings passed to all modified calls, since error_report() appends one. Signed-off-by: Jack Schwartz <jack.schwartz@oracle.com> Reviewed-by: Daniel Kiper <daniel.kiper@oracle.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2018-03-07multiboot: Use header names when displaying fieldsJack Schwartz1-8/+8
Refer to field names when displaying fields in printf and debug statements. Signed-off-by: Jack Schwartz <jack.schwartz@oracle.com> Reviewed-by: Daniel Kiper <daniel.kiper@oracle.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2018-03-07multiboot: Remove unused variables from multiboot.cJack Schwartz1-6/+0
Remove unused variables: mh_mode_type, mh_width, mh_height, mh_depth Signed-off-by: Jack Schwartz <jack.schwartz@oracle.com> Reviewed-by: Daniel Kiper <daniel.kiper@oracle.com> Reviewed-by: Prasad J Pandit <pjp@fedoraproject.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2018-03-07multiboot: bss_end_addr can be zeroJack Schwartz1-8/+10
The multiboot spec (https://www.gnu.org/software/grub/manual/multiboot/), section 3.1.3, allows for bss_end_addr to be zero. A zero bss_end_addr signifies there is no .bss section. Suggested-by: Daniel Kiper <daniel.kiper@oracle.com> Signed-off-by: Jack Schwartz <jack.schwartz@oracle.com> Reviewed-by: Daniel Kiper <daniel.kiper@oracle.com> Reviewed-by: Prasad J Pandit <pjp@fedoraproject.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2018-03-07RISC-V Build InfrastructureMichael Clark1-0/+11
This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive Freedom U Series RISC-V MachineMichael Clark1-0/+339
This provides a RISC-V Board compatible with the the SiFive Freedom U SDK. The following machine is implemented: - 'sifive_u'; CLINT, PLIC, UART, device-tree Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive Freedom E Series RISC-V MachineMichael Clark1-0/+234
This provides a RISC-V Board compatible with the the SiFive Freedom E SDK. The following machine is implemented: - 'sifive_e'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V PRCI BlockMichael Clark1-0/+89
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V UART DeviceMichael Clark1-0/+176
QEMU model of the UART on the SiFive E300 and U500 series SOCs. BBL supports the SiFive UART for early console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The SiFive UART implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V VirtIO MachineMichael Clark1-0/+420
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V Test FinisherMichael Clark1-0/+93
Test finisher memory mapped device used to exit simulation. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V Spike MachinesMichael Clark1-0/+376
RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V Instruction Set Simulator. The following machines are implemented: - 'spike_v1.9.1'; HTIF console, config-string, Privileged ISA Version 1.9.1 - 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10 Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V PLIC BlockMichael Clark1-0/+505
The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V CLINT BlockMichael Clark1-0/+254
The CLINT (Core Local Interruptor) device provides real-time clock, timer and interprocessor interrupts based on SiFive's CLINT specification. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V HART ArrayMichael Clark1-0/+89
Holds the state of a heterogenous array of RISC-V hardware threads. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V HTIF ConsoleMichael Clark1-0/+258
HTIF (Host Target Interface) provides console emulation for QEMU. HTIF allows identical copies of BBL (Berkeley Boot Loader) and linux to run on both Spike and QEMU. BBL provides HTIF console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The HTIT chardev implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07Add symbol table callback interface to load_elfMichael Clark1-2/+16
The RISC-V HTIF (Host Target Interface) console device requires access to the symbol table to locate the 'tohost' and 'fromhost' symbols. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-06tpm: convert tpm_tis.c to use trace-eventsStefan Berger2-53/+61
Leave the DEBUG_TIS for more debugging and convert to use if (DEBUG_TIS) rather than #if DEBUG_TIS where it is being used. Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-06tpm: convert tpm_emulator.c to use trace-eventsStefan Berger2-22/+37
Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-06tpm: convert tpm_util.c to use trace-eventsStefan Berger2-17/+19
Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-06tpm: convert tpm_passthrough.c to use trace-eventsStefan Berger2-10/+7
Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-06tpm: convert tpm_crb.c to use trace-eventsStefan Berger2-12/+10
Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-06misc: don't use hwaddr as a type in trace eventsDaniel P. Berrangé1-2/+2
Use types that are defined by QEMU in trace events caused build failures for the UST trace backend: In file included from trace-ust-all.c:13:0: trace-ust-all.h:11844:206: error: unknown type name ‘hwaddr’ It only knows about C built-in types, and any types that are pulled in from includs of qemu-common.h and lttng/tracepoint.h. This does not include the 'hwaddr' type, so replace it with a uint64_t which is what exec/hwaddr.h defines 'hwaddr' as. This fixes the build failure introduced by commit 9eb8040c2d2b38e1a40bb6129b1b668fa178fcab Author: Peter Maydell <peter.maydell@linaro.org> Date: Fri Mar 2 10:45:39 2018 +0000 hw/misc/tz-ppc: Model TrustZone peripheral protection controller Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180306134317.836-1-berrange@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-06use g_path_get_basename instead of basenameJulia Suvorova3-3/+3
basename(3) and dirname(3) modify their argument and may return pointers to statically allocated memory which may be overwritten by subsequent calls. g_path_get_basename and g_path_get_dirname have no such issues, and therefore more preferable. Signed-off-by: Julia Suvorova <jusual@mail.ru> Message-Id: <1519888086-4207-1-git-send-email-jusual@mail.ru> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-06openpic_kvm: drop address_space_to_flatview callPaolo Bonzini1-4/+0
The MemoryListener is registered on address_space_memory, there is not much to assert. This currently works because the callback is invoked only once when the listener is registered, but section->fv is the _new_ FlatView, not the old one on later calls and that would break. This confines address_space_to_flatview to exec.c and memory.c. Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-06scsi: Remove automatic creation of SCSI controllers with -drive if=scsiThomas Huth6-75/+3
Automatic creation of SCSI controllers for "-drive if=scsi" for x86 machines was quite a bad idea (see description of commit f778a82f0c179 for details). This is marked as deprecated since QEMU v2.9.0, and as far as I know, nobody complained that this is still urgently required anymore. Time to remove this now. Suggested-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1519123357-13225-1-git-send-email-thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-06g364fb: fix DirtyBitmapSnapshot leakPaolo Bonzini1-0/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-06Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell1-9/+1
Block layer patches # gpg: Signature made Mon 05 Mar 2018 17:45:51 GMT # gpg: using RSA key 7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (38 commits) block: Fix NULL dereference on empty drive error qcow2: Replace align_offset() with ROUND_UP() block/ssh: Add basic .bdrv_truncate() block/ssh: Make ssh_grow_file() blocking block/ssh: Pull ssh_grow_file() from ssh_create() qemu-img: Make resize error message more general qcow2: make qcow2_co_create2() a coroutine_fn block: rename .bdrv_create() to .bdrv_co_create_opts() Revert "IDE: Do not flush empty CDROM drives" block: test blk_aio_flush() with blk->root == NULL block: add BlockBackend->in_flight counter block: extract AIO_WAIT_WHILE() from BlockDriverState aio: rename aio_context_in_iothread() to in_aio_context_home_thread() docs: document how to use the l2-cache-entry-size parameter specs/qcow2: Fix documentation of the compressed cluster descriptor iotest 033: add misaligned write-zeroes test via truncate block: fix write with zero flag set and iovector provided block: Drop unused .bdrv_co_get_block_status() vvfat: Switch to .bdrv_co_block_status() vpc: Switch to .bdrv_co_block_status() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # include/block/block.h
2018-03-06adb: add trace-events for monitoring keyboard/mouse during bus enumerationMark Cave-Ayland3-0/+14
This is useful to help diagnose problems related to address clashes during MacOS 9 boot. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-03-06PPC: e500: Fix duplicate kernel load and device tree overlapDavid Engraf1-46/+70
This patch fixes an incorrect behavior when the -kernel argument has been specified without -bios. In this case the kernel was loaded twice. At address 32M as a raw image and afterwards by load_elf/load_uimage at the corresponding load address. In this case the region for the device tree and the raw kernel image may overlap. The patch fixes the behavior by loading the kernel image once with load_elf/load_uimage and skips loading the raw image. When here do not use bios_name/size for the kernel and use a more generic name called payload_name/size. New in v3: dtb must be stored between kernel and initrd because Linux can handle the dtb only within the first 64MB. Add a comment to clarify the behavior. Signed-off-by: David Engraf <david.engraf@sysgo.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-03-06hw/ppc/spapr,e500: Use new property "stdout-path" for boot consoleNikunj A Dadhania2-0/+14
Linux kernel commit 2a9d832cc9aae21ea827520fef635b6c49a06c6d (of: Add bindings for chosen node, stdout-path) deprecated chosen property "linux,stdout-path" and "stdout". Introduce the new property "stdout-path" and continue supporting the older property to remain compatible with existing/older firmware. This older property can be deprecated after 5 years. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-03-06ppc/spapr-caps: Define the pseries-2.12-sxxm machine typeSuraj Jitindar Singh2-0/+28
The sxxm (speculative execution exploit mitigation) machine type is a variant of the 2.12 machine type with workarounds for speculative execution vulnerabilities enabled by default. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-03-06ppc/spapr-caps: Convert cap-ibs to custom spapr-capSuraj Jitindar Singh2-67/+28
Convert cap-ibs (indirect branch speculation) to a custom spapr-cap type. All tristate caps have now been converted to custom spapr-caps, so remove the remaining support for them. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> [dwg: Don't explicitly list "?"/help option, trust convention] [dwg: Fold tristate removal into here, to not break bisect] [dwg: Fix minor style problems] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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