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2016-10-04STM32F2xx: Add the SPI deviceAlistair Francis2-0/+226
Add the STM32F2xx SPI device. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 8197811d5c94f814fa67c6a33ca2f7fd0aa97432.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-22imx: Use 'const char', not 'char const'Peter Maydell1-1/+1
'char const' means the same thing as 'const char', but we use the former in only a handful of places and we use the latter over six thousand times. Switch the imx reg_name() functions to bring them in line with everything else. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-07-14ast2400: pretend DMAs are done for U-bootCédric Le Goater1-0/+4
U-boot does SPI timing calibration using DMA tranfers. To let the initialization continue, we fake success by setting the DMA status of the Interrupt Control Register. For the moment, DMA support is not required as it is not used in normal operation. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1467994016-11678-4-git-send-email-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-07-14ast2400: replace aspeed_smc_is_implemented()Cédric Le Goater1-20/+15
aspeed_smc_is_implemented() filters invalid registers in a peculiar way. Let's remove it and open code the if conditions. It serves the same purpose, the aesthetic is better, and new registers can easily be added. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1467994016-11678-3-git-send-email-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-07-04ast2400: add SPI flash slavesCédric Le Goater1-3/+147
Each controller on the ast2400 has a memory range on which it maps its flash module slaves. Each slave is assigned a memory segment for its mapping that can be changed at bootime with the Segment Address Register. This is not supported in the current implementation so we are using the defaults provided by the specs. Each SPI flash slave can then be accessed in two modes: Command and User. When in User mode, accesses to the memory segment of the slaves are translated in SPI transfers. When in Command mode, the HW generates the SPI commands automatically and the memory segment is accessed as if doing a MMIO. Other SPI controllers call that mode linear addressing mode. For this purpose, we are adding below each crontoller an array of structs gathering for each SPI flash module, a segment rank, a MemoryRegion to handle the memory accesses and the associated SPI slave device, which should be a m25p80. Only the User mode is supported for now but we are preparing ground for the Command mode. The framework is sufficient to support Linux. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1467138270-32481-8-git-send-email-clg@kaod.org [PMM: Use g_new0() rather than g_malloc0()] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-07-04ast2400: add SMC controllers (FMC and SPI)Cédric Le Goater2-0/+327
The Aspeed AST2400 soc includes a static memory controller for the BMC which supports NOR, NAND and SPI flash memory modules. This controller has two modes : the SMC for the legacy interface which supports only one module and the FMC for the new interface which supports up to five modules. The AST2400 also includes a SPI only controller used for the host firmware, commonly called BIOS on Intel. It can be used in three mode : a SPI master, SPI slave and SPI pass-through Below is the initial framework for the SMC controller (FMC mode only) and the SPI controller: the sysbus object, MMIO for registers configuration and controls. Each controller has a SPI bus and a configurable number of CS lines for SPI flash slaves. The differences between the controllers are small, so they are abstracted using indirections on the register numbers. Only SPI flash modules are supported. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1467138270-32481-7-git-send-email-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added one missing error_propagate] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-07-04ssi: change ssi_slave_init to be a realize opsCédric Le Goater1-3/+3
This enables qemu to handle late inits and report errors. All the SSI slave routine names were changed accordingly. Code was modified to handle errors when possible (m25p80 and ssi-sd) Tested with the m25p80 slave object. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1467138270-32481-2-git-send-email-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-05-19hw: explicitly include qemu/log.hPaolo Bonzini2-0/+2
Move the inclusion out of hw/hw.h, most files do not need it. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-12i.MX: Add the Freescale SPI ControllerJean-Christophe DUBOIS2-0/+455
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-29hw: Clean up includesPeter Maydell1-0/+1
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-38-git-send-email-peter.maydell@linaro.org
2016-01-29arm devices: Clean up includesPeter Maydell2-0/+2
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-36-git-send-email-peter.maydell@linaro.org
2016-01-29arm: Clean up includesPeter Maydell2-0/+2
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-13-git-send-email-peter.maydell@linaro.org
2016-01-21xilinx_spips: Separate the state struct into a headerAlistair Francis1-42/+4
Separate out the XilinxSPIPS struct into a separate header file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21ssi: Move ssi.h into a separate directoryAlistair Francis4-4/+4
Move the ssi.h include file into the ssi directory. While touching the code also fix the typdef lines as checkpatch complains. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07arm: Use g_new() & friends where that makes obvious senseMarkus Armbruster1-2/+1
g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer, for two reasons. One, it catches multiplication overflowing size_t. Two, it returns T * rather than void *, which lets the compiler catch more type errors. This commit only touches allocations with size arguments of the form sizeof(T). Coccinelle semantic patch: @@ type T; @@ -g_malloc(sizeof(T)) +g_new(T, 1) @@ type T; @@ -g_try_malloc(sizeof(T)) +g_try_new(T, 1) @@ type T; @@ -g_malloc0(sizeof(T)) +g_new0(T, 1) @@ type T; @@ -g_try_malloc0(sizeof(T)) +g_try_new0(T, 1) @@ type T; expression n; @@ -g_malloc(sizeof(T) * (n)) +g_new(T, n) @@ type T; expression n; @@ -g_try_malloc(sizeof(T) * (n)) +g_try_new(T, n) @@ type T; expression n; @@ -g_malloc0(sizeof(T) * (n)) +g_new0(T, n) @@ type T; expression n; @@ -g_try_malloc0(sizeof(T) * (n)) +g_try_new0(T, n) @@ type T; expression p, n; @@ -g_realloc(p, sizeof(T) * (n)) +g_renew(T, p, n) @@ type T; expression p, n; @@ -g_try_realloc(p, sizeof(T) * (n)) +g_try_renew(T, p, n) @@ type T; expression n; @@ -(T *)g_new(T, n) +g_new(T, n) @@ type T; expression n; @@ -(T *)g_new0(T, n) +g_new0(T, n) @@ type T; expression p, n; @@ -(T *)g_renew(T, p, n) +g_renew(T, p, n) Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 1440524394-15640-1-git-send-email-armbru@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-19omap: Fix warnings from SparseStefan Weil1-1/+2
Sparse report: arm/omap1.c:1015:9: warning: returning void-valued expression arm/omap1.c:1084:9: warning: returning void-valued expression arm/omap1.c:1178:9: warning: returning void-valued expression arm/omap1.c:1287:9: warning: returning void-valued expression arm/omap1.c:1382:9: warning: returning void-valued expression arm/omap1.c:1650:9: warning: returning void-valued expression arm/omap1.c:1778:9: warning: returning void-valued expression arm/omap1.c:1985:9: warning: returning void-valued expression arm/omap1.c:210:9: warning: returning void-valued expression arm/omap1.c:2213:9: warning: returning void-valued expression arm/omap1.c:2352:9: warning: returning void-valued expression arm/omap1.c:2447:9: warning: returning void-valued expression arm/omap1.c:2640:9: warning: returning void-valued expression arm/omap1.c:317:9: warning: returning void-valued expression arm/omap1.c:3413:13: warning: returning void-valued expression arm/omap1.c:3414:13: warning: returning void-valued expression arm/omap1.c:3415:14: warning: returning void-valued expression arm/omap1.c:3589:9: warning: returning void-valued expression arm/omap1.c:443:9: warning: returning void-valued expression arm/omap1.c:588:9: warning: returning void-valued expression arm/omap1.c:860:9: warning: returning void-valued expression arm/omap2.c:1362:9: warning: returning void-valued expression arm/omap2.c:450:9: warning: returning void-valued expression arm/omap2.c:695:9: warning: returning void-valued expression arm/omap2.c:760:9: warning: returning void-valued expression hw/char/omap_uart.c:115:9: warning: returning void-valued expression hw/display/omap_dss.c:1019:9: warning: returning void-valued expression hw/display/omap_dss.c:215:9: warning: returning void-valued expression hw/display/omap_dss.c:380:9: warning: returning void-valued expression hw/display/omap_dss.c:739:9: warning: returning void-valued expression hw/display/omap_dss.c:931:9: warning: returning void-valued expression hw/dma/omap_dma.c:139:5: warning: returning void-valued expression hw/dma/omap_dma.c:1505:9: warning: returning void-valued expression hw/dma/omap_dma.c:1860:9: warning: returning void-valued expression hw/gpio/omap_gpio.c:116:9: warning: returning void-valued expression hw/misc/omap_gpmc.c:627:9: warning: returning void-valued expression hw/misc/omap_l4.c:85:9: warning: returning void-valued expression hw/misc/omap_sdrc.c:95:9: warning: returning void-valued expression hw/misc/omap_tap.c:98:9: warning: returning void-valued expression hw/sd/omap_mmc.c:409:9: warning: returning void-valued expression hw/ssi/omap_spi.c:229:9: warning: returning void-valued expression hw/timer/omap_gptimer.c:447:9: warning: returning void-valued expression Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-08-15ssi: xilinx_spi: Initialise CS GPIOs as NULLPeter Crosthwaite1-1/+1
To properly indicate they are unconnected. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-05-28ssi: Name the CS GPIOPeter Crosthwaite1-2/+2
To get it out of the default GPIO list. This allows child devices to use the un-named GPIO namespace without having to be SSI aware. That is, there is no more need for machines to know about the obscure policy where GPIO 0 is the SSI chip-select and GPIO 1..N are the concrete class GPIOs (defined locally as 0..N-1). This is most notable in stellaris, which uses a device which has both SSI and concrete level GPIOs. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-05-13savevm: Remove all the unneeded version_minimum_id_old (arm)Juan Quintela4-6/+2
After commit 767adce2d, they are redundant. This way we don't assign them except when needed. Once there, there were lots of cases where the ".fields" indentation was wrong: .fields = (VMStateField []) { and .fields = (VMStateField []) { Change all the combinations to: .fields = (VMStateField[]){ The biggest problem (apart from aesthetics) was that checkpatch complained when we copy&pasted the code from one place to another. Signed-off-by: Juan Quintela <quintela@redhat.com> [PMM: fixed minor conflict, corrected commit message typos] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-05pl022: fix buffer overun on invalid state loadMichael S. Tsirkin1-0/+14
CVE-2013-4530 pl022.c did not bounds check tx_fifo_head and rx_fifo_head after loading them from file and before they are used to dereference array. Reported-by: Michael S. Tsirkin <mst@redhat.com Reported-by: Anthony Liguori <anthony@codemonkey.ws> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2014-03-12ssi: Convert legacy SSI_BUS -> BUS castsPeter Crosthwaite1-4/+5
Remove two legacy ->qbus style casts from TYPE_SSI_BUS to TYPE_BUS in ssi.c. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [AF: Convert one missing ->qbus and rename parent field] Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-12ssi: Convert legacy SSI_SLAVE -> DEVICE castsPeter Crosthwaite1-1/+1
Convert legacy ->qdev style casts from TYPE_SSI_SLAVE to TYPE_DEVICE. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [AF: Introduce local DeviceState variable for transition to QOM realize] Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-10hw/ssi/xilinx_spips.c: Avoid shifting left into sign bitPeter Maydell1-2/+2
Add missing 'U' suffix to avoid shifting left into sign bit of a signed integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392988008-15938-4-git-send-email-peter.maydell@linaro.org
2013-07-29xilinx_spi: QOM cast cleanupAndreas Färber1-11/+16
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29pl022: QOM cast cleanupAndreas Färber1-8/+13
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29pl022: Rename pl022_state to PL022StateAndreas Färber1-36/+36
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-04hw/s*: pass owner to memory_region_init* functionsPaolo Bonzini3-4/+6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-04memory: add owner argument to initialization functionsPaolo Bonzini4-5/+5
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-06-07qdev: Drop FROM_QBUS() macroAndreas Färber1-1/+1
Use QOM cast macros I2C_BUS(), SSI_BUS(), PCI_BUS() instead. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-03xilinx_spips: lqspi: Fix byte/misaligned accessPeter Crosthwaite1-14/+17
The LQSPI bus attachment supports byte/halfword and misaligned accesses. Fixed. Refactored the LQSPI cache to be byte-wise instead of word wise accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 5ec47b13563ad2d22105a1f26186d7756718394b.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: lqspi: Push more data to tx-fifoPeter Crosthwaite1-4/+7
Do 16 words per fifo flush. Increases performance and decreases debug verbosity. This data depth has no real hardware analogue, so just go with something that has reasonable performance. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 5621ee4621941d3639b5cacfdec26bd3148f31d5.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: Multiple debug verbosity levelsPeter Crosthwaite1-28/+42
The debug printfs on every SPI operation is extremely verbose. Add a second level of debug for this. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: f63478b8e5b29cc011cdc10e29f8537bb2fc2b5e.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: Debug msgs for Snoop statePeter Crosthwaite1-0/+3
This is worth keeping track of when debugging the device model. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: d3b44ecf23d671798b062eee5dc362c716ea54cd.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: Fix striping behaviourPeter Crosthwaite1-21/+63
The QSPI controller was using byte-wide stripes when striping across the two flashes in dual parallel mode. The real hardware however uses individual bit striping. QEMU misbehaves in the (corner) case where data is written/read in dual-parallel mode and read/written back in single mode. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 718a61df1bf746ec06f6da44d12f8317af7b08ce.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: Fix CTRL register RW bitsPeter Crosthwaite1-2/+3
The CTRL register was RAZ/WI on some of the RW bits. Even though the function behind these bits is invalid in QEMU, they should still be guest accessible. Fix. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: b7aaad93163ce4af0c428635804ac7b77a567b25.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: lqspi: Dont touch config registerPeter Crosthwaite1-6/+6
The LQSPI mode is supposed to work via the automatic CS mode feature rather than manipulate CS lines itself. Now that auto CS is implemented remove LQSPIs CS mode override logic. There is still a need to manipulate the U_PAGE bit in LQSPI config register to implement dual-stack mode however. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 000c8dd54df09523f17052638100722ef0f5a3af.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: Implement automatic CSPeter Crosthwaite1-4/+14
Implement the automatic CS control feature. If the MANUAL_CS bit is cleared then the chip select stay de-asserted as long as the tx FIFO is empty. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 1d67383adc42761af715a93f161344b9284dfc9a.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: Add automatic start supportPeter Crosthwaite1-1/+2
SPI has a mode where it automatically starts based on tx fifo occupancy. Implemented. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: f4e9accb5de87b526fff6ed937f63278db76533b.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: Trash LQ page cache on mode changePeter Crosthwaite1-1/+24
Invalidate the LQSPI cached page when transitioning into LQSPI mode. Otherwise there is a possibility that the controller will return stale data to the guest when transitioning back to LQ_MODE after a page program. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 677490a6ee1953fe5d366e599d665de645ac84db.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: Fix QSPI FIFO sizePeter Crosthwaite1-2/+25
QSPI has a bigger FIFO than the regular SPI controller. Differentiate between the two with correct FIFO sizes for each. This is the first piece of class data for SPIPS, so this patch sees the creation of the XilinxSPIPSClass definition and assoicated QOM constructs. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: acee25dd5e203215cbc15ca5d3cb5d5b2efebe7b.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: Add verbose LQSPI debug outputPeter Crosthwaite1-1/+4
You really need this is you want to track a guest banging on LQSPI. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 26e508da4af11058d37daa777064c9e5c2a69abb.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: Inhibit interrupts in LQSPI modePeter Crosthwaite1-1/+6
The real hardware does not produce interrupts in LQSPI mode. Inhibit generation of interrupts when the LQ_MODE bit is set. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: dff794a06872009ea7e5733ce6adcff94d18bbd0.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: Make interrupts clear on readPeter Crosthwaite1-0/+4
By default these interrupts are clear on read. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 999ff0091ed3cc3969a431bf55c00ef934cecc8e.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03xilinx_spips: seperate SPI and QSPI as two classesPeter Crosthwaite1-14/+55
Make SPI and QSPI different classes. QSPIPS is setup as a child of SPIPS. Only QSPI has the LQSPI functionality, so move all that to the child class. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 2cdd0cadb5ba77ca02fde5cae627852dc9a64c71.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-08hw: move SSI controllers to hw/ssi/, configure via default-configs/Paolo Bonzini4-0/+1357
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08hw: move target-independent files to subdirectoriesPaolo Bonzini3-0/+484
This patch tackles all files that are compiled once, moving them to subdirectories of hw/. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08hw: make subdirectories for devicesPaolo Bonzini1-0/+0
Prepare the new directory structure. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2024-09-27 11:16:53 +0000