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2024-07-21aspeed/smc: Fix possible integer overflowCédric Le Goater1-2/+1
Coverity reports a possible integer overflow because routine aspeeed_smc_hclk_divisor() has a codepath returning 0, which could lead to an integer overflow when computing variable 'hclk_shift' in the caller aspeed_smc_dma_calibration(). The value passed to aspeed_smc_hclk_divisor() is always between 0 and 15 and, in this case, there is always a matching hclk divisor. Remove the return 0 and use g_assert_not_reached() instead. Fixes: Coverity CID 1547822 Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-06-16aspeed/smc: Add AST2700 supportJamin Lin1-1/+233
AST2700 fmc/spi controller's address decoding unit is 64KB and only bits [31:16] are used for decoding. Introduce seg_to_reg and reg_to_seg handlers for ast2700 fmc/spi controller. In addition, adds ast2700 fmc, spi0, spi1, and spi2 class init handler. AST2700 is a 64 bits quad core CPUs(Cortex-a35). Introduce a new "aspeed_2700_smc_flash_ops" and set its valid "max_access_size" 8 for 64 bits data format access. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-06-16aspeed/smc: support different memory region ops for SMC flash regionJamin Lin1-1/+13
It set "aspeed_smc_flash_ops" struct which containing read and write callbacks to be used when I/O is performed on the SMC flash region. And it set the valid max_access_size 4 by default for all ASPEED SMC models. However, the valid max_access_size 4 only support 32 bits CPUs. To support all ASPEED SMC model, introduce a new "const MemoryRegionOps *" attribute in AspeedSMCClass and use it in aspeed_smc_flash_realize function. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-06-16aspeed/smc: support 64 bits dma dram addressJamin Lin1-8/+43
AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM Side Address High Part(0x7C)" register to support 64 bits dma dram address. Add helper routines functions to compute the dma dram address, new features and update trace-event to support 64 bits dram address. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-06-16aspeed/smc: support dma start length and 1 byte length unitJamin Lin1-8/+35
DMA length is from 1 byte to 32MB for AST2600 and AST10x0 and DMA length is from 4 bytes to 32MB for AST2500. In other words, if "R_DMA_LEN" is 0, it should move at least 1 byte data for AST2600 and AST10x0 and 4 bytes data for AST2500. To support all ASPEED SOCs, adds dma_start_length parameter to store the start length, add helper routines function to compute the dma length and update DMA_LENGTH mask to "1FFFFFF" to support dma 1 byte length unit for AST2600 and AST1030. Currently, only supports dma length 4 bytes aligned. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-06-16aspeed/smc: correct device descriptionJamin Lin1-3/+3
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2024-06-16aspeed/smc: Reintroduce "dram-base" property for AST2700Cédric Le Goater1-0/+1
The Aspeed SMC device model use to have a 'sdram_base' property. It was removed by commit d177892d4a48 ("aspeed/smc: Remove unused "sdram-base" property") because previous changes simplified the DMA transaction model to use an offset in RAM and not the physical address. The AST2700 SoC has larger address space (64-bit) and a new register DMA DRAM Side Address High Part (0x7C) is introduced to deal with the high bits of the DMA address. To be able to compute the offset of the DMA transaction, as done on the other SoCs, we will need to know where the DRAM is mapped in the address space. Re-introduce a "dram-base" property to hold this value. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-03-19aspeed/smc: Only wire flash devices at resetCédric Le Goater1-0/+9
The Aspeed machines have many Static Memory Controllers (SMC), up to 8, which can only drive flash memory devices. Commit 27a2c66c92ec ("aspeed/smc: Wire CS lines at reset") tried to ease the definitions of these devices by allowing flash devices from the command line to be attached to a SSI bus. For that, the wiring of the CS lines of the Aspeed SMC controller was moved at reset. Two assumptions are made though, first that the device has a SSI_GPIO_CS GPIO line, which is not always the case, and second that it is a flash device. Correct this problem by ensuring that the devices attached to the bus are of the correct flash type. This fixes a QEMU abort when devices without a CS line, such as the max111x, are passed on the command line. While at it, export TYPE_M25P80 used in the Xilinx Versal Virtual machine. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2228 Fixes: 27a2c66c92ec ("aspeed/smc: Wire CS lines at reset") Reported-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> [ clg: minor fixes in the commit log ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
2023-12-30hw/ssi: Constify VMStateRichard Henderson1-1/+1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-56-richard.henderson@linaro.org>
2023-09-01aspeed/smc: Wire CS lines at resetCédric Le Goater1-0/+8
Currently, a set of default flash devices is created at machine init and drives defined on the QEMU command line are associated to the FMC and SPI controllers in sequence : -drive file<file>,format=raw,if=mtd -drive file<file1>,format=raw,if=mtd The CS lines are wired in the same creation loop. This makes a strong assumption on the ordering and is not very flexible since only a limited set of flash devices can be defined : 1 FMC + 1 or 2 SPI, which is less than what the SoC really supports. A better alternative would be to define the flash devices on the command line using a blockdev attached to a CS line of a SSI bus : -blockdev node-name=fmc0,driver=file,filename=./flash.img -device mx66u51235f,cs=0x0,bus=ssi.0,drive=fmc0 However, user created flash devices are not correctly wired to their SPI controller and consequently can not be used by the machine. Fix that and wire the CS lines of all available devices when the SSI bus is reset. Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-03-02aspeed/smc: Replace SysBus IRQs with GPIO linesCédric Le Goater1-4/+1
It's cleaner and removes the curious '+ 1' required to skip the DMA IRQ line of the controller. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-10-24aspeed/smc: Cache AspeedSMCClassCédric Le Goater1-5/+4
Store a reference on the AspeedSMC class under the flash object and use it when accessing the flash contents. Avoiding the class cast checkers in these hot paths improves performance by 10% when running the aspeed avocado tests. Message-Id: <20220923084803.498337-7-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30aspeed/smc: Fix potential overflowCédric Le Goater1-2/+2
Coverity warns that "ssi_transfer(s->spi, 0U) << 8 * i" might overflow because the expression is evaluated using 32-bit arithmetic and then used in a context expecting a uint64_t. Fixes: Coverity CID 1487244 Message-Id: <20220628165512.1133590-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-02aspeed/smc: Add AST1030 supportSteven Lee1-0/+157
AST1030 spi controller's address decoding unit is 1MB that is identical to ast2600, but fmc address decoding unit is 512kb. Introduce seg_to_reg and reg_to_seg handlers for ast1030 fmc controller. In addition, add ast1030 fmc, spi1, and spi2 class init handler. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220401083850.15266-3-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-08aspeed/smc: Fix error logCédric Le Goater1-1/+1
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220307071856.1410731-7-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-08aspeed/smc: Let the SSI core layer define the bus nameCédric Le Goater1-1/+1
If no id is provided, qdev automatically assigns an unique name with the following pattern "<type>.<index>" which avoids bus name collision when using multiple buses. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220307071856.1410731-6-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-08aspeed/smc: Rename 'max_peripherals' to 'cs_num_max'Cédric Le Goater1-21/+21
The naming makes more sense in a SPI controller model. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220307071856.1410731-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-08aspeed/smc: Remove 'num_cs' fieldCédric Le Goater1-7/+0
It is not used anymore. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220307071856.1410731-4-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-08aspeed/smc: Use max number of CE instead of 'num_cs'Cédric Le Goater1-4/+4
The Aspeed SMC model uses the 'num_cs' field to allocate resources fitting the number of devices of the machine. This is a small optimization without real need in the controller. Simplify modelling and use the max_peripherals field instead. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220307071856.1410731-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-26aspeed/smc: Add an address mask on segment registersCédric Le Goater1-0/+11
Only a limited set of bits are used for decoding the Start and End addresses of the mapping window of a flash device. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-22aspeed/smc: Use a container for the flash mmio address spaceCédric Le Goater1-4/+7
Because AddressSpaces must not be sysbus-mapped, commit e9c568dbc225 ("hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use alias") introduced an alias for the flash mmio region. Using a container is cleaner. Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-Id: <20211018132609.160008-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Dump address offset in trace eventsCédric Le Goater1-3/+3
The register index is currently printed and this is confusing. Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Introduce a new addr_width() class handlerCédric Le Goater1-7/+12
The AST2400 SPI controller has a transitional HW interface and it stores the address width currently in use in a different register than all the other SMC controllers. It needs special handling when working in 4B mode. Make it clear through a class handler. This also removes another use of the segments array. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Add default reset valuesCédric Le Goater1-25/+27
This simplifies the reset handler and has the benefit to remove some "bad" use of the segments array as an identifier of the controller model. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: QOMify AspeedSMCFlashCédric Le Goater1-8/+68
AspeedSMCFlash is a small structure representing the AHB memory window through which the contents of a flash device can be accessed with MMIOs. Introduce an AspeedSMCFlash SysBusDevice model and attach the associated memory region to the newly instantiated objects. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Rename AspeedSMCFlash 'id' to 'cs'Cédric Le Goater1-15/+15
'cs' is a more appropriate name to index SPI flash devices. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Remove the 'size' attribute from AspeedSMCFlashCédric Le Goater1-3/+2
AspeedSMCFlash::size is only used to compute the initial size of the boot_rom region. Not very useful, so directly call memory_region_size() instead. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Drop AspeedSMCController structureCédric Le Goater1-383/+478
The characteristics of the Aspeed controllers are described in a AspeedSMCController structure which is redundant with the AspeedSMCClass. Move all attributes under the class and adapt the code to use class attributes instead. This is a large change but it is functionally equivalent. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Stop using the model name for the memory regionsCédric Le Goater1-15/+10
There is no real reason to use this name. It's simply nice to have in the monitor output but it's a burden for the following patch which removes the AspeedSMCController structure describing the controller. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Introduce aspeed_smc_error() helperCédric Le Goater1-52/+45
It unifies the errors reported by the Aspeed SMC model and also removes some use of ctrl->name which will help us for the next patches. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-12aspeed/smc: Add watchdog Control/Status RegistersCédric Le Goater1-1/+18
The Aspeed SoCs have a dual boot function for firmware fail-over recovery. The system auto-reboots from the second flash if the main flash does not boot successfully within a certain amount of time. This function is called alternate boot (ABR) in the FMC controllers. On AST2400/AST2500, ABR is enabled by hardware strapping in SCU70 to enable the 2nd watchdog timer, on AST2600, through register SCU510. If the boot on the the main flash succeeds, the firmware should disable the 2nd watchdog timer. If not, the BMC is reset and the CE0 and CE1 mappings are swapped to restart the BMC from the 2nd flash. On the AST2600, the ABR registers controlling the 2nd watchdog timer were moved from the watchdog register to the FMC controller and the FMC model should be able to control WDT2 through its own register set. This requires more work. For now, add dummy read/write handlers to let the FW disable the 2nd watchdog without error. Reviewed-by: Peter Delevoryas <pdel@fb.com> Reported-by: Peter Delevoryas <pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-05Merge remote-tracking branch ↵Peter Maydell1-1/+0
'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging Trivial patches pull request 20210503 # gpg: Signature made Mon 03 May 2021 09:34:56 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.1-pull-request: (23 commits) hw/rx/rx-gdbsim: Do not accept invalid memory size docs: More precisely describe memory-backend-*::id's user scripts: fix generation update-binfmts templates docs/system: Document the removal of "compat" property for POWER CPUs mc146818rtc: put it into the 'misc' category Do not include exec/address-spaces.h if it's not really necessary Do not include cpu.h if it's not really necessary Do not include hw/boards.h if it's not really necessary Do not include sysemu/sysemu.h if it's not really necessary hw: Do not include qemu/log.h if it is not necessary hw: Do not include hw/irq.h if it is not necessary hw: Do not include hw/sysbus.h if it is not necessary hw: Remove superfluous includes of hw/hw.h ui: Fix memory leak in qemu_xkeymap_mapping_table() hw/usb: Constify VMStateDescription hw/display/qxl: Constify VMStateDescription hw/arm: Constify VMStateDescription vmstate: Constify some VMStateDescriptions Fix typo in CFI build documentation hw/pcmcia: Do not register PCMCIA type if not required ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-02Do not include exec/address-spaces.h if it's not really necessaryThomas Huth1-1/+0
Stop including exec/address-spaces.h in files that don't need it. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-5-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-01aspeed/smc: Add extra controls to request DMACédric Le Goater1-7/+67
The AST2600 SPI controllers have a set of bits to request/grant DMA access. Add a new SMC feature for these controllers and use it to check access to the DMA registers. Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20210407171637.777743-16-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01aspeed/smc: Add a 'features' attribute to the object classCédric Le Goater1-19/+25
It will simplify extensions of the SMC model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20210407171637.777743-15-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use aliasPhilippe Mathieu-Daudé1-3/+4
The flash mmio region is exposed as an AddressSpace. AddressSpaces must not be sysbus-mapped, therefore map the region using an alias. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [ clg : Fix DMA_FLASH_ADDR() ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210312182851.1922972-3-f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210407171637.777743-6-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01aspeed/smc: Remove unused "sdram-base" propertyCédric Le Goater1-1/+0
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210407171637.777743-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-05-01aspeed/smc: Use the RAM memory region for DMAsCédric Le Goater1-2/+1
Instead of passing the memory address space region, simply use the RAM memory region instead. This simplifies RAM accesses. This patch breaks migration compatibility. Fixes: c4e1f0b48322 ("aspeed/smc: Add support for DMAs") Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210407171637.777743-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-12-10hw/ssi/aspeed_smc: Rename 'max_slaves' variable as 'max_peripherals'Philippe Mathieu-Daudé1-26/+27
In order to use inclusive terminology, rename max_slaves as max_peripherals. Patch generated using: $ sed -i s/slave/peripheral/ \ hw/ssi/aspeed_smc.c include/hw/ssi/aspeed_smc.h One line in aspeed_smc_read() has been manually tweaked to pass checkpatch. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201012124955.3409127-2-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-12-10aspeed/smc: Add support for address lane disablementCédric Le Goater1-7/+18
The controller can be configured to disable or enable address and data byte lanes when issuing commands. This is useful in read command mode to send SPI NOR commands that don't have an address space, such as RDID. It's a good way to have a unified read operation for registers and flash contents accesses. A new SPI driver proposed by Aspeed makes use of this feature. Add support for address lanes to start with. We will do the same for the data lanes if they are controlled one day. Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20201120161547.740806-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-09-01aspeed/smc: Open AHB window of the second chip of the AST2600 FMC controllerCédric Le Goater1-1/+1
This change works around the HW default values to be able to test the Tacoma board with -kernel command line option. This was required when we had both flash chips enabled in the device tree, otherwise Linux would fail to probe the entire controller leaving it with no rootfs. Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20200819100956.2216690-20-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-09-01aspeed/smc: Fix max_slaves of the legacy SMC deviceCédric Le Goater1-1/+1
The legacy controller only has one slave. Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20200819100956.2216690-8-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-09-01aspeed/smc: Fix MemoryRegionOps definitionCédric Le Goater1-2/+0
Unaligned access support is a leftover from the initial commit. There is no such need on this device register mapping. Remove it. Cc: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20200819100956.2216690-7-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-06-15ssi: ssi_auto_connect_slaves() never does anything, dropMarkus Armbruster1-1/+0
ssi_auto_connect_slaves(parent, cs_line, bus) iterates over @parent's QOM children @dev of type TYPE_SSI_SLAVE. It puts these on @bus, and sets cs_line[] to qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0). Suspicious: there is no protection against overrunning cs_line[]. Turns out it's safe because ssi_auto_connect_slaves() never finds any such children. Its called by realize methods of some (but not all) devices providing an SSI bus, and gets passed the device. SSI slave devices are always created with ssi_create_slave_no_init(), optionally via ssi_create_slave(). This adds them to their SSI bus. It doesn't set their QOM parent. ssi_create_slave_no_init() is always immediately followed by qdev_init_nofail(), with no QOM parent assigned, so device_set_realized() puts the device into the /machine/unattached/ orphanage. None become QOM children of a device providing an SSI bus. ssi_auto_connect_slaves() was added in commit b4ae3cfa57 "ssi: Add slave autoconnect helper". I can't see which slaves it was supposed to connect back then. Cc: Alistair Francis <alistair@alistair23.me> Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-23-armbru@redhat.com>
2020-03-23aspeed/smc: Fix DMA support for AST2600Cédric Le Goater1-2/+13
Recent firmwares uses SPI DMA transfers in U-Boot to load the different images (kernel, initrd, dtb) in the SoC DRAM. The AST2600 FMC model is missing the masks to be applied on the DMA registers which resulted in incorrect values. Fix that and wire the SPI controllers which have DMA support on the AST2600. Fixes: bcaa8ddd081c ("aspeed/smc: Add AST2600 support") Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20200320053923.20565-1-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-17aspeed/smc: Fix number of dummy cycles for FAST_READ_4 commandGuenter Roeck1-1/+1
The Linux kernel recently started using FAST_READ_4 commands. This results in flash read failures. At the same time, the m25p80 emulation is seen to read 8 more bytes than expected. Adjusting the expected number of dummy cycles to match FAST_READ fixes the problem. Fixes: f95c4bffdc4c ("aspeed/smc: snoop SPI transfers to fake dummy cycles") Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-12aspeed/smc: Fix User mode select/unselect schemeCédric Le Goater1-16/+23
The Aspeed SMC Controller can operate in different modes : Read, Fast Read, Write and User modes. When the User mode is configured, it selects automatically the SPI slave device until the CE_STOP_ACTIVE bit is set to 1. When any other modes are configured the device is unselected. The HW logic handles the chip select automatically when the flash is accessed through its AHB window. When configuring the CEx Control Register, the User mode logic to select and unselect the slave is incorrect and data corruption can be seen on machines using two chips, witherspoon and romulus. Rework the handler setting the CEx Control Register to fix this issue. Fixes: 7c1c69bca43c ("ast2400: add SMC controllers (FMC and SPI)") Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20200206112645.21275-3-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-12aspeed/smc: Add some tracingCédric Le Goater1-0/+17
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200206112645.21275-2-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau1-1/+1
The following patch will need to handle properties registration during class_init time. Let's use a device_class_set_props() setter. spatch --macro-file scripts/cocci-macro-file.h --sp-file ./scripts/coccinelle/qdev-set-props.cocci --keep-comments --in-place --dir . @@ typedef DeviceClass; DeviceClass *d; expression val; @@ - d->props = val + device_class_set_props(d, val) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200110153039.1379601-20-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-16aspeed/smc: Add AST2600 timings registersCédric Le Goater1-3/+14
Each CS has its own Read Timing Compensation Register on newer SoCs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-13-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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