riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-04-29	riscv: sifive_e: Support changing CPU type	Corey Wharton	1	-2/+3
2020-04-29	hw/riscv: Generate correct "mmu-type" for 32-bit machines	Bin Meng	3	-0/+12
2020-04-29	riscv/sifive_u: Add a serial property to the sifive_u machine	Bin Meng	1	-0/+20
2020-04-29	riscv/sifive_u: Add a serial property to the sifive_u SoC	Alistair Francis	1	-1/+7
2020-04-29	riscv/sifive_u: Fix up file ordering	Alistair Francis	1	-54/+54
2020-04-29	various: Remove suspicious '\' character outside of #define in C code	Philippe Mathieu-Daudé	1	-1/+1
2020-03-17	Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging	Peter Maydell	2	-6/+5
2020-03-17	hw/riscv: Let devices own the MemoryRegion they create	Philippe Mathieu-Daudé	2	-4/+4
2020-03-17	hw/riscv: Use memory_region_init_rom() with read-only regions	Philippe Mathieu-Daudé	1	-3/+2
2020-03-16	riscv: sifive_u: Update BIOS_FILENAME for 32-bit	Bin Meng	1	-1/+5
2020-03-03	Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...	Peter Maydell	5	-7/+15
2020-02-28	hw: Make MachineClass::is_default a boolean type	Philippe Mathieu-Daudé	1	-1/+1
2020-02-27	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	Anup Patel	5	-7/+14
2020-02-27	riscv: virt: Allow PCI address 0	Bin Meng	1	-0/+1
2020-02-10	riscv: virt: Use Goldfish RTC device	Anup Patel	2	-0/+17
2020-02-10	riscv/virt: Add syscon reboot and poweroff DT nodes	Anup Patel	1	-4/+22
2020-01-29	hw/core/loader: Let load_elf() populate a field with CPU-specific flags	Aleksandar Markovic	1	-2/+2
2020-01-27	Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging	Peter Maydell	4	-4/+4
2020-01-24	qdev: set properties with device_class_set_props()	Marc-André Lureau	4	-4/+4
2020-01-16	riscv/sifive_u: fix a memory leak in soc_realize()	Pan Nengyuan	1	-0/+1
2020-01-08	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	Philippe Mathieu-Daudé	2	-2/+2
2019-11-25	hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()	Zhuang, Siwei (Data61, Kensington NSW)	5	-9/+12
2019-11-25	RISC-V: virt: This is a "sifive,test1" test finisher	Palmer Dabbelt	1	-1/+4
2019-11-14	riscv/virt: Increase flash size	Alistair Francis	1	-1/+1
2019-10-28	riscv/boot: Fix possible memory leak	Alistair Francis	1	-7/+4
2019-10-28	riscv/virt: Jump to pflash if specified	Alistair Francis	1	-1/+10
2019-10-28	riscv/virt: Add the PFlash CFI01 device	Alistair Francis	2	-0/+87
2019-10-28	riscv/virt: Manually define the machine	Alistair Francis	1	-6/+24
2019-10-28	riscv/sifive_u: Add the start-in-flash property	Alistair Francis	1	-1/+29
2019-10-28	riscv/sifive_u: Manually define the machine	Alistair Francis	1	-13/+31
2019-10-28	riscv/sifive_u: Add QSPI memory region	Alistair Francis	1	-0/+8
2019-10-28	riscv/sifive_u: Add L2-LIM cache memory	Alistair Francis	1	-0/+16
2019-10-28	riscv: sifive_u: Add ethernet0 to the aliases node	Bin Meng	1	-1/+4
2019-10-28	riscv: hw: Drop "clock-frequency" property of cpu nodes	Bin Meng	3	-6/+0
2019-09-17	riscv: sifive_u: Update model and compatible strings in device tree	Bin Meng	1	-2/+3
2019-09-17	riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet	Bin Meng	1	-23/+1
2019-09-17	riscv: sifive_u: Fix broken GEM support	Bin Meng	2	-4/+21
2019-09-17	riscv: sifive_u: Instantiate OTP memory with a serial number	Bin Meng	1	-0/+9
2019-09-17	riscv: sifive: Implement a model for SiFive FU540 OTP	Bin Meng	2	-0/+192
2019-09-17	riscv: sifive_u: Change UART node name in device tree	Bin Meng	1	-1/+1
2019-09-17	riscv: sifive_u: Update UART base addresses and IRQs	Bin Meng	1	-2/+2
2019-09-17	riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes	Bin Meng	1	-3/+4
2019-09-17	riscv: sifive_u: Add PRCI block to the SoC	Bin Meng	1	-1/+23
2019-09-17	riscv: sifive_u: Generate hfclk and rtcclk nodes	Bin Meng	1	-0/+23
2019-09-17	riscv: sifive: Implement PRCI model for FU540	Bin Meng	2	-0/+170
2019-09-17	riscv: sifive_u: Update PLIC hart topology configuration string	Bin Meng	1	-3/+4
2019-09-17	riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC	Bin Meng	1	-25/+67
2019-09-17	riscv: sifive_u: Set the minimum number of cpus to 2	Bin Meng	1	-1/+4
2019-09-17	riscv: hart: Add a "hartid-base" property to RISC-V hart array	Bin Meng	1	-1/+2
2019-09-17	riscv: hart: Extract hart realize to a separate routine	Bin Meng	1	-13/+20