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2019-11-25hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)5-9/+12
2019-11-25RISC-V: virt: This is a "sifive,test1" test finisherPalmer Dabbelt1-1/+4
2019-11-14riscv/virt: Increase flash sizeAlistair Francis1-1/+1
2019-10-28riscv/boot: Fix possible memory leakAlistair Francis1-7/+4
2019-10-28riscv/virt: Jump to pflash if specifiedAlistair Francis1-1/+10
2019-10-28riscv/virt: Add the PFlash CFI01 deviceAlistair Francis2-0/+87
2019-10-28riscv/virt: Manually define the machineAlistair Francis1-6/+24
2019-10-28riscv/sifive_u: Add the start-in-flash propertyAlistair Francis1-1/+29
2019-10-28riscv/sifive_u: Manually define the machineAlistair Francis1-13/+31
2019-10-28riscv/sifive_u: Add QSPI memory regionAlistair Francis1-0/+8
2019-10-28riscv/sifive_u: Add L2-LIM cache memoryAlistair Francis1-0/+16
2019-10-28riscv: sifive_u: Add ethernet0 to the aliases nodeBin Meng1-1/+4
2019-10-28riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng3-6/+0
2019-09-17riscv: sifive_u: Update model and compatible strings in device treeBin Meng1-2/+3
2019-09-17riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng1-23/+1
2019-09-17riscv: sifive_u: Fix broken GEM supportBin Meng2-4/+21
2019-09-17riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng1-0/+9
2019-09-17riscv: sifive: Implement a model for SiFive FU540 OTPBin Meng2-0/+192
2019-09-17riscv: sifive_u: Change UART node name in device treeBin Meng1-1/+1
2019-09-17riscv: sifive_u: Update UART base addresses and IRQsBin Meng1-2/+2
2019-09-17riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng1-3/+4
2019-09-17riscv: sifive_u: Add PRCI block to the SoCBin Meng1-1/+23
2019-09-17riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng1-0/+23
2019-09-17riscv: sifive: Implement PRCI model for FU540Bin Meng2-0/+170
2019-09-17riscv: sifive_u: Update PLIC hart topology configuration stringBin Meng1-3/+4
2019-09-17riscv: sifive_u: Update hart configuration to reflect the real FU540 SoCBin Meng1-25/+67
2019-09-17riscv: sifive_u: Set the minimum number of cpus to 2Bin Meng1-1/+4
2019-09-17riscv: hart: Add a "hartid-base" property to RISC-V hart arrayBin Meng1-1/+2
2019-09-17riscv: hart: Extract hart realize to a separate routineBin Meng1-13/+20
2019-09-17riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng2-15/+9
2019-09-17riscv: sifive_e: prci: Update the PRCI register block sizeBin Meng1-1/+1
2019-09-17riscv: sifive_e: prci: Fix a typo of hfxosccfg register programmingBin Meng1-1/+1
2019-09-17riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}Bin Meng3-43/+42
2019-09-17riscv: sifive_u: Remove the unnecessary include of prci headerBin Meng1-1/+0
2019-09-17riscv: hw: Remove the unnecessary include of target/riscv/cpu.hBin Meng3-3/+0
2019-09-17riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) insteadBin Meng3-9/+13
2019-09-17riscv: hw: Change create_fdt() to return voidBin Meng2-14/+8
2019-09-17riscv: hw: Remove not needed PLIC properties in device treeBin Meng2-4/+0
2019-09-17riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cellBin Meng2-21/+21
2019-09-17riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng3-8/+0
2019-09-17riscv: hw: Remove duplicated "hw/hw.h" inclusionBin Meng2-2/+0
2019-09-17riscv: sifive_test: Add reset functionalityBin Meng1-0/+4
2019-09-17riscv: Resolve full path of the given bios imageBin Meng1-3/+3
2019-09-17riscv: Add a helper routine for finding firmwareBin Meng1-7/+15
2019-09-17riscv: plic: Remove unused interrupt functionsAlistair Francis1-12/+0
2019-09-17riscv: sifive_u: Fix clock-names property for ethernet nodeGuenter Roeck1-1/+1
2019-09-17riscv: sivive_u: Add dummy serial clock and aliases entry for uartGuenter Roeck1-2/+17
2019-09-17riscv: sifive_u: Add support for loading initrdGuenter Roeck1-3/+17
2019-08-16Include sysemu/sysemu.h a lot lessMarkus Armbruster4-0/+4
2019-08-16Include hw/boards.h a bit lessMarkus Armbruster1-1/+1