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2020-09-09hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng1-0/+39
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2-0/+16
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2-0/+24
2020-09-09hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2-0/+31
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng3-0/+319
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng3-0/+4
2020-09-09hw/riscv: hart: Add a new 'resetvec' propertyBin Meng1-0/+3
2020-09-09riscv: sifive_test: Allow 16-bit writes to memory regionNathan Chancellor1-1/+1
2020-09-08configure: do not include dependency flags in QEMU_CFLAGS and LIBSPaolo Bonzini1-1/+1
2020-08-27opentitan: Rename memmap enum constantsEduardo Habkost1-42/+42
2020-08-25hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel1-227/+299
2020-08-25hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel1-74/+158
2020-08-25hw/riscv: Add helpers for RISC-V multi-socket NUMA machinesAnup Patel2-0/+243
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel4-14/+16
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel5-12/+16
2020-08-21hw/riscv: spike: Change the default bios to use generic platform imageBin Meng1-2/+7
2020-08-21hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng2-4/+4
2020-08-21hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng1-0/+22
2020-08-21meson: convert hw/arch*Marc-André Lureau2-16/+19
2020-08-21trace: switch position of headers to what Meson requiresPaolo Bonzini1-0/+1
2020-07-22hw/riscv: sifive_e: Correct debug block sizeBin Meng1-1/+1
2020-07-21hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster1-0/+1
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng3-3/+3
2020-07-13RISC-V: Support 64 bit start addressAtish Patra2-2/+10
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra4-15/+72
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra4-32/+63
2020-07-13riscv: Unify Qemu's reset vector code pathAtish Patra4-76/+52
2020-07-13hw/riscv: virt: Sort the SoC memmap table entriesBin Meng1-3/+3
2020-07-10error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster3-12/+4
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster5-11/+11
2020-07-10qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster3-8/+4
2020-07-02hw/riscv: Allow 64 bit access to SiFive CLINTAlistair Francis1-1/+1
2020-07-02riscv: plic: Add a couple of mising sifive_plic_update callsJessica Clarke1-1/+2
2020-07-02riscv: plic: Honour source prioritiesJessica Clarke1-5/+12
2020-07-02riscv_hart: Fix riscv_harts_realize() error API violationsMarkus Armbruster1-9/+5
2020-07-02riscv/sifive_u: Fix sifive_u_soc_realize() error API violationsMarkus Armbruster1-3/+9
2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng1-0/+4
2020-06-19hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng1-2/+2
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng1-8/+31
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng2-7/+9
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng1-0/+7
2020-06-19hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng1-6/+8
2020-06-19hw/riscv: sifive_u: Add reset functionalityBin Meng1-1/+23
2020-06-19hw/riscv: sifive_gpio: Do not blindly trigger output IRQsBin Meng1-1/+3
2020-06-19hw/riscv: sifive_u: Hook a GPIO controllerBin Meng1-2/+41
2020-06-19hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng1-11/+19
2020-06-19hw/riscv: sifive_gpio: Clean up the codesBin Meng1-8/+5
2020-06-19hw/riscv: sifive_u: Generate device tree node for OTPBin Meng1-0/+11
2020-06-19hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng1-6/+1
2020-06-19hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng1-15/+14
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