aboutsummaryrefslogtreecommitdiff
path: root/hw/riscv
AgeCommit message (Expand)AuthorFilesLines
2023-09-29hw/riscv: opentitan: Fixup local variables shadowingAlistair Francis1-1/+1
2023-09-11hw/riscv/virt.c: fix non-KVM --enable-debug buildDaniel Henrique Barboza1-3/+3
2023-09-11hw/riscv: virt: Fix riscv,pmu DT node pathConor Dooley1-1/+1
2023-09-11target/riscv: select KVM AIA in riscv virt machineYong-Xuan Wang1-31/+63
2023-09-11target/riscv: support the AIA device emulation with KVM enabledYong-Xuan Wang1-153/+137
2023-09-08riscv: spelling fixesMichael Tokarev2-3/+3
2023-09-01hw/sd: Introduce a "sd-card" SPI variant modelCédric Le Goater1-2/+1
2023-08-11hw/riscv/virt.c: change 'aclint' TCG checkDaniel Henrique Barboza1-7/+13
2023-07-19hw/riscv: Fix typo field in error_reportZhao Liu1-2/+2
2023-07-10hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not setDaniel Henrique Barboza1-7/+7
2023-07-10hw/riscv: virt: Convert fdt_load_addr to uint64_tLakshmi Bai Raja Subramanian1-1/+1
2023-07-10riscv: Generate devicetree only after machine initialization is completeGuenter Roeck1-11/+11
2023-07-10hw/riscv/virt: Restrict ACLINT to TCGPhilippe Mathieu-Daudé1-8/+10
2023-07-10hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.Tommy Wu2-2/+16
2023-07-08hw/riscv/virt.c: fix typo in 'aia' descriptionDaniel Henrique Barboza1-1/+1
2023-06-26hw/riscv: Validate cluster and NUMA node boundaryGavin Shan2-0/+4
2023-06-13riscv/virt: Support using pflash via -blockdev optionSunil V L1-3/+5
2023-06-13hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"Sunil V L1-32/+21
2023-06-13hw/riscv: qemu crash when NUMA nodes exceed available CPUsYin Wang1-0/+6
2023-06-13hw/riscv/opentitan: Correct OpenTitanState parent type/sizePhilippe Mathieu-Daudé1-1/+2
2023-06-13hw/riscv/opentitan: Explicit machine type definitionPhilippe Mathieu-Daudé1-3/+7
2023-06-13hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definitionPhilippe Mathieu-Daudé1-1/+1
2023-06-13hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macroPhilippe Mathieu-Daudé1-12/+9
2023-06-13hw/riscv/opentitan: Rename machine_[class]_init() functionsPhilippe Mathieu-Daudé1-4/+4
2023-06-05bulk: Remove pointless QOM castsPhilippe Mathieu-Daudé1-5/+5
2023-05-05hw/riscv: Add signature dump function for spike to run ACT testsWeiwei Li1-0/+13
2023-03-22*: Add missing includes of qemu/error-report.hRichard Henderson3-0/+3
2023-03-06hw/riscv/virt.c: Initialize the ACPI tablesSunil V L1-0/+4
2023-03-06hw/riscv/virt: virt-acpi-build.c: Add RHCT TableSunil V L1-0/+78
2023-03-06hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADTSunil V L1-0/+34
2023-03-06hw/riscv/virt: Enable basic ACPI infrastructureSunil V L3-0/+306
2023-03-06hw/riscv/virt: Add memmap pointer to RiscVVirtStateSunil V L1-0/+2
2023-03-06hw/riscv/virt: Add a switch to disable ACPISunil V L1-0/+29
2023-03-06hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fieldsSunil V L1-0/+5
2023-03-06riscv: Correctly set the device-tree entry 'mmu-type'Alexandre Ghiti1-8/+11
2023-03-05hw/riscv/virt.c: add cbo[mz]-block-size fdt propertiesAnup Patel1-0/+11
2023-03-01hw/riscv: Move the dtb load bits outside of create_fdt()Bin Meng2-31/+29
2023-03-01hw/riscv: Skip re-generating DT nodes for a given DTBBin Meng2-0/+2
2023-03-01hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus()Daniel Henrique Barboza1-3/+4
2023-02-16hw/riscv/boot.c: make riscv_load_initrd() staticDaniel Henrique Barboza1-40/+40
2023-02-16hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza7-42/+19
2023-02-16hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza7-9/+29
2023-02-07hw/riscv: virt: Simplify virt_{get,set}_aclint()Bin Meng1-4/+2
2023-02-07hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza5-16/+31
2023-02-07hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza5-16/+40
2023-02-07hw/riscv/boot.c: calculate fdt size after fdt_pack()Daniel Henrique Barboza1-4/+6
2023-02-07hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'Daniel Henrique Barboza1-9/+9
2023-02-07hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms'Daniel Henrique Barboza1-217/+217
2023-02-07hw/riscv/virt.c: calculate socket count once in create_fdt_imsic()Daniel Henrique Barboza1-15/+19
2023-02-07hw/riscv: boot: Don't use CSRs if they are disabledAlistair Francis1-0/+9
generated by cgit v1.1 at 2024-12-26 15:36:39 +0000