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AgeCommit message (Expand)AuthorFilesLines
2021-05-11hw/riscv: Fix OT IBEX reset vectorAlexander Wagner1-1/+1
2021-05-11hw/riscv: Enable VIRTIO_VGA for RISC-V virt machineAlistair Francis1-0/+1
2021-05-11hw/opentitan: Update the interrupt layoutAlistair Francis1-4/+4
2021-05-11hw/riscv: Connect Shakti UART to Shakti platformVijai Kumar K1-0/+8
2021-05-11riscv: Add initial support for Shakti C machineVijai Kumar K3-0/+184
2021-05-11hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]Bin Meng1-1/+1
2021-05-02Do not include exec/address-spaces.h if it's not really necessaryThomas Huth2-2/+0
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth6-6/+0
2021-05-02hw: Do not include hw/irq.h if it is not necessaryThomas Huth1-1/+0
2021-03-22hw/riscv: microchip_pfsoc: Map EMMC/SD mux registerBin Meng1-0/+6
2021-03-22hw/riscv: allow ramfb on virtAsherah Connor1-0/+3
2021-03-22hw/riscv: Add fw_cfg support to virtAsherah Connor2-0/+31
2021-03-11Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-docs-xen-upda...Peter Maydell1-10/+10
2021-03-10hw/riscv: migrate fdt field to generic MachineStateAlex Bennée1-10/+10
2021-03-09qtest: delete superfluous inclusions of qtest.hChen Qun1-1/+0
2021-03-04hw/riscv: virt: Map high mmio for PCIeBin Meng1-2/+33
2021-03-04hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng1-0/+10
2021-03-04hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng1-7/+7
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng6-37/+19
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng2-2/+42
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng2-0/+54
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis4-19/+17
2021-01-16hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng1-5/+1
2021-01-16RISC-V: Place DTB at 3GB boundary instead of 4GBAtish Patra1-4/+4
2020-12-17riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis1-24/+57
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis4-34/+24
2020-12-17hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis1-25/+30
2020-12-17hw/riscv: spike: Remove compile time XLEN checksAlistair Francis1-21/+24
2020-12-17hw/riscv: virt: Remove compile time XLEN checksAlistair Francis1-15/+17
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis4-28/+34
2020-12-17riscv: virt: Remove target macro conditionalsAlistair Francis1-1/+1
2020-12-17riscv: spike: Remove target macro conditionalsAlistair Francis1-1/+1
2020-12-17hw/riscv: Expand the is 32-bit check to support more CPUsAlistair Francis1-1/+11
2020-12-17hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool1-0/+21
2020-12-17hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel1-0/+15
2020-12-15vl: make qemu_get_machine_opts staticPaolo Bonzini2-8/+4
2020-12-10vl: extract softmmu/datadir.cPaolo Bonzini1-0/+1
2020-12-10riscv: do not use ram_size globalPaolo Bonzini1-2/+3
2020-11-03hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng1-0/+6
2020-11-03hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng1-6/+44
2020-11-03hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng1-1/+10
2020-11-03hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng2-3/+7
2020-11-03hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng2-5/+9
2020-11-03hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng2-0/+19
2020-11-03hw/riscv: microchip_pfsoc: Document where to look at the SoC memory mapsBin Meng1-0/+18
2020-11-03hw/riscv: virt: Allow passing custom DTBAnup Patel1-7/+20
2020-11-03hw/riscv: sifive_u: Allow passing custom DTBAnup Patel1-8/+20
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis6-15/+42
2020-10-22hw/riscv: Add a riscv_is_32_bit() functionAlistair Francis1-0/+9
2020-10-22hw/riscv: Return the end address of the loaded firmwareAlistair Francis1-11/+17
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