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AgeCommit message (Expand)AuthorFilesLines
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis6-15/+42
2020-10-22hw/riscv: Add a riscv_is_32_bit() functionAlistair Francis1-0/+9
2020-10-22hw/riscv: Return the end address of the loaded firmwareAlistair Francis1-11/+17
2020-10-22hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis1-5/+13
2020-09-25load_elf: Remove unused address variables from callersBALATON Zoltan1-4/+4
2020-09-22sifive_u: Register "start-in-flash" as class propertyEduardo Habkost1-8/+8
2020-09-22sifive_e: Register "revb" as class propertyEduardo Habkost1-5/+6
2020-09-18sifive_u: Rename memmap enum constantsEduardo Habkost1-78/+78
2020-09-18sifive_e: Rename memmap enum constantsEduardo Habkost1-41/+41
2020-09-09hw/riscv: Sort the Kconfig options in alphabetical orderBin Meng1-29/+29
2020-09-09hw/riscv: Drop CONFIG_SIFIVEBin Meng1-9/+5
2020-09-09hw/riscv: Always build riscv_hart.cBin Meng2-10/+1
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng4-102/+2
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng5-197/+4
2020-09-09hw/riscv: Move riscv_htif model to hw/charBin Meng4-266/+1
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng7-529/+9
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng8-272/+10
2020-09-09hw/riscv: Move sifive_gpio model to hw/gpioBin Meng5-406/+2
2020-09-09hw/riscv: Move sifive_u_otp model to hw/miscBin Meng3-192/+1
2020-09-09hw/riscv: Move sifive_u_prci model to hw/miscBin Meng3-170/+1
2020-09-09hw/riscv: Move sifive_e_prci model to hw/miscBin Meng4-127/+2
2020-09-09hw/riscv: sifive_u: Connect a DMA controllerBin Meng2-0/+31
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng6-16/+28
2020-09-09hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng1-0/+14
2020-09-09hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng1-0/+39
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2-0/+16
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2-0/+24
2020-09-09hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2-0/+31
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng3-0/+319
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng3-0/+4
2020-09-09hw/riscv: hart: Add a new 'resetvec' propertyBin Meng1-0/+3
2020-09-09riscv: sifive_test: Allow 16-bit writes to memory regionNathan Chancellor1-1/+1
2020-09-08configure: do not include dependency flags in QEMU_CFLAGS and LIBSPaolo Bonzini1-1/+1
2020-08-27opentitan: Rename memmap enum constantsEduardo Habkost1-42/+42
2020-08-25hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel1-227/+299
2020-08-25hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel1-74/+158
2020-08-25hw/riscv: Add helpers for RISC-V multi-socket NUMA machinesAnup Patel2-0/+243
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel4-14/+16
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel5-12/+16
2020-08-21hw/riscv: spike: Change the default bios to use generic platform imageBin Meng1-2/+7
2020-08-21hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng2-4/+4
2020-08-21hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng1-0/+22
2020-08-21meson: convert hw/arch*Marc-André Lureau2-16/+19
2020-08-21trace: switch position of headers to what Meson requiresPaolo Bonzini1-0/+1
2020-07-22hw/riscv: sifive_e: Correct debug block sizeBin Meng1-1/+1
2020-07-21hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster1-0/+1
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng3-3/+3
2020-07-13RISC-V: Support 64 bit start addressAtish Patra2-2/+10
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra4-15/+72
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra4-32/+63
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