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AgeCommit message (Expand)AuthorFilesLines
2019-09-17riscv: sifive_u: Remove the unnecessary include of prci headerBin Meng1-1/+0
2019-09-17riscv: hw: Remove the unnecessary include of target/riscv/cpu.hBin Meng3-3/+0
2019-09-17riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) insteadBin Meng3-9/+13
2019-09-17riscv: hw: Change create_fdt() to return voidBin Meng2-14/+8
2019-09-17riscv: hw: Remove not needed PLIC properties in device treeBin Meng2-4/+0
2019-09-17riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cellBin Meng2-21/+21
2019-09-17riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng3-8/+0
2019-09-17riscv: hw: Remove duplicated "hw/hw.h" inclusionBin Meng2-2/+0
2019-09-17riscv: sifive_test: Add reset functionalityBin Meng1-0/+4
2019-09-17riscv: Resolve full path of the given bios imageBin Meng1-3/+3
2019-09-17riscv: Add a helper routine for finding firmwareBin Meng1-7/+15
2019-09-17riscv: plic: Remove unused interrupt functionsAlistair Francis1-12/+0
2019-09-17riscv: sifive_u: Fix clock-names property for ethernet nodeGuenter Roeck1-1/+1
2019-09-17riscv: sivive_u: Add dummy serial clock and aliases entry for uartGuenter Roeck1-2/+17
2019-09-17riscv: sifive_u: Add support for loading initrdGuenter Roeck1-3/+17
2019-08-16Include sysemu/sysemu.h a lot lessMarkus Armbruster4-0/+4
2019-08-16Include hw/boards.h a bit lessMarkus Armbruster1-1/+1
2019-08-16Include hw/qdev-properties.h lessMarkus Armbruster5-0/+5
2019-08-16Include hw/hw.h exactly where neededMarkus Armbruster7-4/+3
2019-08-16Include migration/vmstate.h lessMarkus Armbruster1-0/+1
2019-08-16Include hw/irq.h a lot lessMarkus Armbruster2-0/+2
2019-08-16Include sysemu/reset.h a lot lessMarkus Armbruster1-0/+1
2019-07-26riscv/boot: Fixup the RISC-V firmware warningAlistair Francis1-4/+8
2019-07-18hw/riscv: Load OpenSBI as the default firmwareAlistair Francis3-6/+66
2019-07-05hw/riscv: Replace global smp variables with machine smp propertiesLike Xu5-6/+18
2019-06-27hw/riscv: Extend the kernel loading supportAlistair Francis1-4/+14
2019-06-27hw/riscv: Add support for loading a firmwareAlistair Francis3-0/+34
2019-06-27hw/riscv: Split out the boot functionsAlistair Francis6-93/+83
2019-06-27riscv: sifive_u: Update the plic hart config to support multicoreBin Meng1-1/+15
2019-06-27riscv: sifive_u: Do not create hard-coded phandles in DTBin Meng1-7/+10
2019-06-25riscv: virt: Add cpu-topology DT node.Atish Patra1-2/+20
2019-06-23RISC-V: Fix a memory leak when realizing a sifive_ePalmer Dabbelt1-7/+6
2019-06-23riscv: virt: Correct pci "bus-range" encodingBin Meng1-1/+1
2019-06-23sifive_prci: Read and write PRCI registersNathaniel Graff1-8/+41
2019-06-12Include qemu/module.h where needed, drop it from qemu-common.hMarkus Armbruster5-0/+5
2019-05-24riscv: spike: Add a generic spike machineAlistair Francis1-1/+105
2019-05-24riscv: virt: Allow specifying a CPU via commandlineAlistair Francis1-1/+2
2019-05-24target/riscv: Remove unused include of riscv_htif.h for virt board riscvJonathan Behrens1-1/+0
2019-05-24SiFive RISC-V GPIO DeviceFabien Chouteau4-2/+422
2019-04-04riscv: plic: Log guest errorsAlistair Francis1-3/+9
2019-04-04riscv: plic: Fix incorrect irq calculationAlistair Francis1-2/+2
2019-03-28Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2-0/+4
2019-03-19riscv: sifive_u: Correct UART0's IRQ in the device treeBin Meng1-1/+1
2019-03-19riscv: sifive_uart: Generate TX interruptBin Meng1-1/+3
2019-03-19riscv: sifive_u: Allow up to 4 CPUs to be createdAlistair Francis1-1/+4
2019-03-19RISC-V: Allow interrupt controllers to claim interruptsMichael Clark1-0/+15
2019-03-19RISC-V: Replace __builtin_popcount with ctpop8 in PLICMichael Clark1-2/+2
2019-03-18kconfig: add CONFIG_MSI_NONBROKENPaolo Bonzini1-0/+1
2019-03-18riscv: plic: Set msi_nonbroken as trueAlistair Francis1-0/+3
2019-03-11riscv/Kconfig: enable PCI_DEVICESDavid Abdurachmanov1-0/+3