index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
hw
/
riscv
Age
Commit message (
Expand
)
Author
Files
Lines
2019-08-16
Include hw/irq.h a lot less
Markus Armbruster
2
-0
/
+2
2019-08-16
Include sysemu/reset.h a lot less
Markus Armbruster
1
-0
/
+1
2019-07-26
riscv/boot: Fixup the RISC-V firmware warning
Alistair Francis
1
-4
/
+8
2019-07-18
hw/riscv: Load OpenSBI as the default firmware
Alistair Francis
3
-6
/
+66
2019-07-05
hw/riscv: Replace global smp variables with machine smp properties
Like Xu
5
-6
/
+18
2019-06-27
hw/riscv: Extend the kernel loading support
Alistair Francis
1
-4
/
+14
2019-06-27
hw/riscv: Add support for loading a firmware
Alistair Francis
3
-0
/
+34
2019-06-27
hw/riscv: Split out the boot functions
Alistair Francis
6
-93
/
+83
2019-06-27
riscv: sifive_u: Update the plic hart config to support multicore
Bin Meng
1
-1
/
+15
2019-06-27
riscv: sifive_u: Do not create hard-coded phandles in DT
Bin Meng
1
-7
/
+10
2019-06-25
riscv: virt: Add cpu-topology DT node.
Atish Patra
1
-2
/
+20
2019-06-23
RISC-V: Fix a memory leak when realizing a sifive_e
Palmer Dabbelt
1
-7
/
+6
2019-06-23
riscv: virt: Correct pci "bus-range" encoding
Bin Meng
1
-1
/
+1
2019-06-23
sifive_prci: Read and write PRCI registers
Nathaniel Graff
1
-8
/
+41
2019-06-12
Include qemu/module.h where needed, drop it from qemu-common.h
Markus Armbruster
5
-0
/
+5
2019-05-24
riscv: spike: Add a generic spike machine
Alistair Francis
1
-1
/
+105
2019-05-24
riscv: virt: Allow specifying a CPU via commandline
Alistair Francis
1
-1
/
+2
2019-05-24
target/riscv: Remove unused include of riscv_htif.h for virt board riscv
Jonathan Behrens
1
-1
/
+0
2019-05-24
SiFive RISC-V GPIO Device
Fabien Chouteau
4
-2
/
+422
2019-04-04
riscv: plic: Log guest errors
Alistair Francis
1
-3
/
+9
2019-04-04
riscv: plic: Fix incorrect irq calculation
Alistair Francis
1
-2
/
+2
2019-03-28
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell
2
-0
/
+4
2019-03-19
riscv: sifive_u: Correct UART0's IRQ in the device tree
Bin Meng
1
-1
/
+1
2019-03-19
riscv: sifive_uart: Generate TX interrupt
Bin Meng
1
-1
/
+3
2019-03-19
riscv: sifive_u: Allow up to 4 CPUs to be created
Alistair Francis
1
-1
/
+4
2019-03-19
RISC-V: Allow interrupt controllers to claim interrupts
Michael Clark
1
-0
/
+15
2019-03-19
RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
Michael Clark
1
-2
/
+2
2019-03-18
kconfig: add CONFIG_MSI_NONBROKEN
Paolo Bonzini
1
-0
/
+1
2019-03-18
riscv: plic: Set msi_nonbroken as true
Alistair Francis
1
-0
/
+3
2019-03-11
riscv/Kconfig: enable PCI_DEVICES
David Abdurachmanov
1
-0
/
+3
2019-03-07
riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directives
Paolo Bonzini
1
-0
/
+13
2019-03-07
kconfig: introduce kconfig files
Paolo Bonzini
1
-0
/
+20
2019-02-11
riscv: Ensure the kernel start address is correctly cast
Alistair Francis
4
-4
/
+4
2019-02-05
hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards
Yang Zhong
1
-11
/
+11
2019-02-05
elf: Add optional function ptr to load_elf() to parse ELF notes
Liam Merwick
4
-4
/
+4
2018-12-20
sifive_uart: Implement interrupt pending register
Nathaniel Graff
1
-5
/
+19
2018-12-20
RISC-V: Enable second UART on sifive_e and sifive_u
Michael Clark
2
-6
/
+4
2018-12-20
RISC-V: Fix PLIC pending bitfield reads
Michael Clark
1
-1
/
+1
2018-12-20
RISC-V: Fix CLINT timecmp low 32-bit writes
Michael Clark
1
-4
/
+4
2018-12-20
sifive_u: Set 'clock-frequency' DT property for SiFive UART
Anup Patel
1
-0
/
+2
2018-12-20
sifive_u: Add clock DT node for GEM ethernet
Anup Patel
1
-1
/
+17
2018-12-20
hw/riscv/virt: Connect the gpex PCIe
Alistair Francis
1
-1
/
+130
2018-12-20
hw/riscv/virt: Adjust memory layout spacing
Alistair Francis
1
-8
/
+8
2018-11-13
hw/riscv/virt: Free the test device tree node name
Alistair Francis
1
-0
/
+1
2018-11-08
riscv: spike: Fix memory leak in the board init
Alistair Francis
1
-3
/
+3
2018-10-17
RISC-V: Don't add NULL bootargs to device-tree
Michael Clark
3
-4
/
+10
2018-10-17
RISC-V: Add missing free for plic_hart_config
Michael Clark
1
-0
/
+2
2018-10-17
RISC-V: Allow setting and clearing multiple irqs
Michael Clark
2
-6
/
+6
2018-09-25
Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-09-24' into...
Peter Maydell
4
-5
/
+5
2018-09-24
Drop "qemu:" prefix from error_report() arguments
Mao Zhongyi
4
-5
/
+5
[next]