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2019-07-05hw/riscv: Replace global smp variables with machine smp propertiesLike Xu5-6/+18
2019-06-27hw/riscv: Extend the kernel loading supportAlistair Francis1-4/+14
2019-06-27hw/riscv: Add support for loading a firmwareAlistair Francis3-0/+34
2019-06-27hw/riscv: Split out the boot functionsAlistair Francis6-93/+83
2019-06-27riscv: sifive_u: Update the plic hart config to support multicoreBin Meng1-1/+15
2019-06-27riscv: sifive_u: Do not create hard-coded phandles in DTBin Meng1-7/+10
2019-06-25riscv: virt: Add cpu-topology DT node.Atish Patra1-2/+20
2019-06-23RISC-V: Fix a memory leak when realizing a sifive_ePalmer Dabbelt1-7/+6
2019-06-23riscv: virt: Correct pci "bus-range" encodingBin Meng1-1/+1
2019-06-23sifive_prci: Read and write PRCI registersNathaniel Graff1-8/+41
2019-06-12Include qemu/module.h where needed, drop it from qemu-common.hMarkus Armbruster5-0/+5
2019-05-24riscv: spike: Add a generic spike machineAlistair Francis1-1/+105
2019-05-24riscv: virt: Allow specifying a CPU via commandlineAlistair Francis1-1/+2
2019-05-24target/riscv: Remove unused include of riscv_htif.h for virt board riscvJonathan Behrens1-1/+0
2019-05-24SiFive RISC-V GPIO DeviceFabien Chouteau4-2/+422
2019-04-04riscv: plic: Log guest errorsAlistair Francis1-3/+9
2019-04-04riscv: plic: Fix incorrect irq calculationAlistair Francis1-2/+2
2019-03-28Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2-0/+4
2019-03-19riscv: sifive_u: Correct UART0's IRQ in the device treeBin Meng1-1/+1
2019-03-19riscv: sifive_uart: Generate TX interruptBin Meng1-1/+3
2019-03-19riscv: sifive_u: Allow up to 4 CPUs to be createdAlistair Francis1-1/+4
2019-03-19RISC-V: Allow interrupt controllers to claim interruptsMichael Clark1-0/+15
2019-03-19RISC-V: Replace __builtin_popcount with ctpop8 in PLICMichael Clark1-2/+2
2019-03-18kconfig: add CONFIG_MSI_NONBROKENPaolo Bonzini1-0/+1
2019-03-18riscv: plic: Set msi_nonbroken as trueAlistair Francis1-0/+3
2019-03-11riscv/Kconfig: enable PCI_DEVICESDavid Abdurachmanov1-0/+3
2019-03-07riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directivesPaolo Bonzini1-0/+13
2019-03-07kconfig: introduce kconfig filesPaolo Bonzini1-0/+20
2019-02-11riscv: Ensure the kernel start address is correctly castAlistair Francis4-4/+4
2019-02-05hw/riscv/Makefile.objs: Create CONFIG_* for riscv boardsYang Zhong1-11/+11
2019-02-05elf: Add optional function ptr to load_elf() to parse ELF notesLiam Merwick4-4/+4
2018-12-20sifive_uart: Implement interrupt pending registerNathaniel Graff1-5/+19
2018-12-20RISC-V: Enable second UART on sifive_e and sifive_uMichael Clark2-6/+4
2018-12-20RISC-V: Fix PLIC pending bitfield readsMichael Clark1-1/+1
2018-12-20RISC-V: Fix CLINT timecmp low 32-bit writesMichael Clark1-4/+4
2018-12-20sifive_u: Set 'clock-frequency' DT property for SiFive UARTAnup Patel1-0/+2
2018-12-20sifive_u: Add clock DT node for GEM ethernetAnup Patel1-1/+17
2018-12-20hw/riscv/virt: Connect the gpex PCIeAlistair Francis1-1/+130
2018-12-20hw/riscv/virt: Adjust memory layout spacingAlistair Francis1-8/+8
2018-11-13hw/riscv/virt: Free the test device tree node nameAlistair Francis1-0/+1
2018-11-08riscv: spike: Fix memory leak in the board initAlistair Francis1-3/+3
2018-10-17RISC-V: Don't add NULL bootargs to device-treeMichael Clark3-4/+10
2018-10-17RISC-V: Add missing free for plic_hart_configMichael Clark1-0/+2
2018-10-17RISC-V: Allow setting and clearing multiple irqsMichael Clark2-6/+6
2018-09-25Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-09-24' into...Peter Maydell4-5/+5
2018-09-24Drop "qemu:" prefix from error_report() argumentsMao Zhongyi4-5/+5
2018-09-05hw/riscv/spike: Set the soc device tree node as a simple-busAlistair Francis1-1/+1
2018-09-05hw/riscv/virtio: Set the soc device tree node as a simple-busAlistair Francis1-1/+1
2018-09-04RISC-V: Use atomic_cmpxchg to update PLIC bitmapsMichael Clark1-27/+22
2018-07-19spike: Fix crash when introspecting the deviceAlistair Francis1-6/+4