Age | Commit message (Expand) | Author | Files | Lines |
2020-08-25 | hw/riscv: virt: Allow creating multiple NUMA sockets | Anup Patel | 1 | -227/+299 |
2020-08-25 | hw/riscv: spike: Allow creating multiple NUMA sockets | Anup Patel | 1 | -74/+158 |
2020-08-25 | hw/riscv: Add helpers for RISC-V multi-socket NUMA machines | Anup Patel | 2 | -0/+243 |
2020-08-25 | hw/riscv: Allow creating multiple instances of PLIC | Anup Patel | 4 | -14/+16 |
2020-08-25 | hw/riscv: Allow creating multiple instances of CLINT | Anup Patel | 5 | -12/+16 |
2020-08-21 | hw/riscv: spike: Change the default bios to use generic platform image | Bin Meng | 1 | -2/+7 |
2020-08-21 | hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u | Bin Meng | 2 | -4/+4 |
2020-08-21 | hw/riscv: sifive_u: Add a dummy L2 cache controller device | Bin Meng | 1 | -0/+22 |
2020-08-21 | meson: convert hw/arch* | Marc-André Lureau | 2 | -16/+19 |
2020-08-21 | trace: switch position of headers to what Meson requires | Paolo Bonzini | 1 | -0/+1 |
2020-07-22 | hw/riscv: sifive_e: Correct debug block size | Bin Meng | 1 | -1/+1 |
2020-07-21 | hw: Mark nd_table[] misuse in realize methods FIXME | Markus Armbruster | 1 | -0/+1 |
2020-07-13 | hw/riscv: Modify MROM size to end at 0x10000 | Bin Meng | 3 | -3/+3 |
2020-07-13 | RISC-V: Support 64 bit start address | Atish Patra | 2 | -2/+10 |
2020-07-13 | riscv: Add opensbi firmware dynamic support | Atish Patra | 4 | -15/+72 |
2020-07-13 | RISC-V: Copy the fdt in dram instead of ROM | Atish Patra | 4 | -32/+63 |
2020-07-13 | riscv: Unify Qemu's reset vector code path | Atish Patra | 4 | -76/+52 |
2020-07-13 | hw/riscv: virt: Sort the SoC memmap table entries | Bin Meng | 1 | -3/+3 |
2020-07-10 | error: Eliminate error_propagate() with Coccinelle, part 1 | Markus Armbruster | 3 | -12/+4 |
2020-07-10 | qom: Put name parameter before value / visitor parameter | Markus Armbruster | 5 | -11/+11 |
2020-07-10 | qdev: Use returned bool to check for qdev_realize() etc. failure | Markus Armbruster | 3 | -8/+4 |
2020-07-02 | hw/riscv: Allow 64 bit access to SiFive CLINT | Alistair Francis | 1 | -1/+1 |
2020-07-02 | riscv: plic: Add a couple of mising sifive_plic_update calls | Jessica Clarke | 1 | -1/+2 |
2020-07-02 | riscv: plic: Honour source priorities | Jessica Clarke | 1 | -5/+12 |
2020-07-02 | riscv_hart: Fix riscv_harts_realize() error API violations | Markus Armbruster | 1 | -9/+5 |
2020-07-02 | riscv/sifive_u: Fix sifive_u_soc_realize() error API violations | Markus Armbruster | 1 | -3/+9 |
2020-06-19 | hw/riscv: sifive_u: Add a dummy DDR memory controller device | Bin Meng | 1 | -0/+4 |
2020-06-19 | hw/riscv: sifive_u: Sort the SoC memmap table entries | Bin Meng | 1 | -2/+2 |
2020-06-19 | hw/riscv: sifive_u: Support different boot source per MSEL pin state | Bin Meng | 1 | -8/+31 |
2020-06-19 | hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 | Bin Meng | 2 | -7/+9 |
2020-06-19 | hw/riscv: sifive_u: Add a new property msel for MSEL pin state | Bin Meng | 1 | -0/+7 |
2020-06-19 | hw/riscv: sifive_u: Rename serial property get/set functions to a generic name | Bin Meng | 1 | -6/+8 |
2020-06-19 | hw/riscv: sifive_u: Add reset functionality | Bin Meng | 1 | -1/+23 |
2020-06-19 | hw/riscv: sifive_gpio: Do not blindly trigger output IRQs | Bin Meng | 1 | -1/+3 |
2020-06-19 | hw/riscv: sifive_u: Hook a GPIO controller | Bin Meng | 1 | -2/+41 |
2020-06-19 | hw/riscv: sifive_gpio: Add a new 'ngpio' property | Bin Meng | 1 | -11/+19 |
2020-06-19 | hw/riscv: sifive_gpio: Clean up the codes | Bin Meng | 1 | -8/+5 |
2020-06-19 | hw/riscv: sifive_u: Generate device tree node for OTP | Bin Meng | 1 | -0/+11 |
2020-06-19 | hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit | Bin Meng | 1 | -6/+1 |
2020-06-19 | hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions | Bin Meng | 1 | -15/+14 |
2020-06-19 | hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions | Bin Meng | 1 | -12/+12 |
2020-06-19 | riscv/opentitan: Connect the UART device | Alistair Francis | 1 | -2/+23 |
2020-06-19 | riscv/opentitan: Connect the PLIC device | Alistair Francis | 1 | -2/+12 |
2020-06-19 | hw/char: Initial commit of Ibex UART | Alistair Francis | 1 | -0/+4 |
2020-06-19 | riscv/opentitan: Fix the ROM size | Alistair Francis | 1 | -1/+2 |
2020-06-19 | sifive_e: Support the revB machine | Alistair Francis | 1 | -4/+30 |
2020-06-15 | qdev: Convert bus-less devices to qdev_realize() with Coccinelle | Markus Armbruster | 4 | -12/+6 |
2020-06-15 | sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2 | Markus Armbruster | 3 | -31/+19 |
2020-06-15 | sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1 | Markus Armbruster | 2 | -8/+6 |
2020-06-15 | sysbus: Convert to sysbus_realize() etc. with Coccinelle | Markus Armbruster | 5 | -6/+6 |