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AgeCommit message (Expand)AuthorFilesLines
2023-02-16hw/riscv/boot.c: make riscv_load_initrd() staticDaniel Henrique Barboza1-40/+40
2023-02-16hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza7-42/+19
2023-02-16hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza7-9/+29
2023-02-07hw/riscv: virt: Simplify virt_{get,set}_aclint()Bin Meng1-4/+2
2023-02-07hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza5-16/+31
2023-02-07hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza5-16/+40
2023-02-07hw/riscv/boot.c: calculate fdt size after fdt_pack()Daniel Henrique Barboza1-4/+6
2023-02-07hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'Daniel Henrique Barboza1-9/+9
2023-02-07hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms'Daniel Henrique Barboza1-217/+217
2023-02-07hw/riscv/virt.c: calculate socket count once in create_fdt_imsic()Daniel Henrique Barboza1-15/+19
2023-02-07hw/riscv: boot: Don't use CSRs if they are disabledAlistair Francis1-0/+9
2023-02-07include/hw/riscv/opentitan: update opentitan IRQsWilfred Mallawa1-40/+40
2023-01-20hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init()Daniel Henrique Barboza1-7/+7
2023-01-20hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()Daniel Henrique Barboza3-6/+6
2023-01-20hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()Daniel Henrique Barboza3-15/+15
2023-01-20hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus()Daniel Henrique Barboza1-9/+9
2023-01-20hw/riscv/sifive_u.c: simplify create_fdt()Daniel Henrique Barboza1-4/+4
2023-01-20hw/riscv/virt.c: simplify create_fdt()Daniel Henrique Barboza1-3/+2
2023-01-20hw/riscv/spike.c: simplify create_fdt()Daniel Henrique Barboza1-3/+1
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza7-13/+8
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza5-10/+8
2023-01-20hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()Daniel Henrique Barboza3-16/+15
2023-01-20hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza5-38/+20
2023-01-20hw/riscv/spike.c: load initrd right after riscv_load_kernel()Daniel Henrique Barboza1-16/+15
2023-01-20hw/riscv/boot.c: exit early if filename is NULL in load functionsDaniel Henrique Barboza1-0/+6
2023-01-20hw/riscv/sifive_u: use 'fdt' from MachineStateDaniel Henrique Barboza1-9/+6
2023-01-20hw/riscv/spike: use 'fdt' from MachineStateDaniel Henrique Barboza1-7/+5
2023-01-20hw/riscv: spike: Decouple create_fdt() dependency to ELF loadingBin Meng1-10/+51
2023-01-20hw/riscv/boot.c: Introduce riscv_find_firmware()Bin Meng1-14/+25
2023-01-20hw/riscv/boot.c: introduce riscv_default_firmware_name()Daniel Henrique Barboza4-23/+21
2023-01-20hw/riscv/boot.c: make riscv_find_firmware() staticDaniel Henrique Barboza1-22/+22
2023-01-20hw/riscv: spike: Remove the out-of-date commentsBin Meng1-5/+0
2023-01-20hw/char: riscv_htif: Move registers from CPUArchState to HTIFStateBin Meng1-2/+1
2023-01-20hw/char: riscv_htif: Drop useless assignment of memory regionBin Meng1-3/+2
2023-01-06hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initializationBin Meng1-2/+0
2023-01-06hw/riscv: virt: Fix the value of "riscv, ndev" in the dtbBin Meng1-1/+2
2023-01-06hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"Bin Meng1-1/+2
2023-01-06hw/riscv: spike: Remove misleading commentsBin Meng1-1/+0
2023-01-06hw/riscv: Sort machines Kconfig options in alphabetical orderBin Meng1-7/+9
2023-01-06hw/riscv: Fix opentitan dependency to SIFIVE_PLICBin Meng1-0/+1
2023-01-06hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLICBin Meng1-5/+0
2023-01-06hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley1-0/+6
2023-01-06hw/riscv: pfsoc: add missing FICs as unimplementedConor Dooley1-52/+63
2023-01-06hw/riscv: virt: Remove the redundant ipi-id propertyAtish Patra1-4/+0
2023-01-06hw/riscv/opentitan: add aon_timer base unimplWilfred Mallawa1-0/+3
2023-01-06hw/riscv/opentitan: bump opentitanWilfred Mallawa1-8/+13
2022-10-27riscv: re-randomize rng-seed on rebootJason A. Donenfeld1-0/+3
2022-10-17hw/riscv: set machine->fdt in spike_board_init()Daniel Henrique Barboza1-0/+6
2022-10-17hw/riscv: set machine->fdt in sifive_u_machine_init()Daniel Henrique Barboza1-0/+3
2022-10-14hw/riscv: virt: Enable booting S-mode firmware from pflashSunil V L2-1/+46
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