aboutsummaryrefslogtreecommitdiff
path: root/hw/riscv/virt.c
AgeCommit message (Expand)AuthorFilesLines
2023-02-07hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza1-1/+2
2023-02-07hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza1-3/+4
2023-02-07hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms'Daniel Henrique Barboza1-217/+217
2023-02-07hw/riscv/virt.c: calculate socket count once in create_fdt_imsic()Daniel Henrique Barboza1-15/+19
2023-01-20hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init()Daniel Henrique Barboza1-7/+7
2023-01-20hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()Daniel Henrique Barboza1-1/+1
2023-01-20hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()Daniel Henrique Barboza1-9/+9
2023-01-20hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus()Daniel Henrique Barboza1-9/+9
2023-01-20hw/riscv/virt.c: simplify create_fdt()Daniel Henrique Barboza1-3/+2
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza1-2/+1
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza1-2/+1
2023-01-20hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()Daniel Henrique Barboza1-6/+5
2023-01-20hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza1-8/+2
2023-01-20hw/riscv/boot.c: introduce riscv_default_firmware_name()Daniel Henrique Barboza1-7/+3
2023-01-06hw/riscv: virt: Fix the value of "riscv, ndev" in the dtbBin Meng1-1/+2
2023-01-06hw/riscv: virt: Remove the redundant ipi-id propertyAtish Patra1-4/+0
2022-10-14hw/riscv: virt: Enable booting S-mode firmware from pflashSunil V L1-1/+17
2022-10-14hw/riscv: virt: Move create_fw_cfg() prior to loading kernelSunil V L1-7/+7
2022-09-07hw/riscv: virt: Add PMU DT node to the device treeAtish Patra1-0/+16
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel1-11/+2
2022-09-07hw/riscv: virt: fix syscon subnode pathsConor Dooley1-2/+2
2022-09-07hw/riscv: virt: fix the plic's address cellsConor Dooley1-0/+2
2022-09-07hw/riscv: virt: fix uart node nameConor Dooley1-1/+1
2022-09-07hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza1-1/+1
2022-09-07hw/riscv: virt: pass random seed to fdtJason A. Donenfeld1-0/+6
2022-06-10hw/riscv: virt: Generate fw_cfg DT node correctlyAtish Patra1-10/+18
2022-05-24hw/riscv: virt: Fix interrupt parent for dynamic platform devicesAnup Patel1-13/+12
2022-05-24hw/riscv: Make CPU config error handling generous (virt/spike)Tsukasa OI1-1/+1
2022-04-29hw/riscv: Enable TPM backendsAlistair Francis1-0/+4
2022-04-29hw/riscv: virt: Add device plug supportAlistair Francis1-0/+35
2022-04-29hw/riscv: virt: Add support for generating platform FDT entriesAlistair Francis1-0/+19
2022-04-29hw/riscv: virt: Create a platform busAlistair Francis1-19/+49
2022-04-29hw/riscv: virt: Add a machine done notifierAlistair Francis1-90/+101
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng1-1/+1
2022-04-22hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabledNiklas Cassel1-2/+8
2022-04-22hw/riscv: virt: Exit if the user provided -bios in combination with KVMRalf Ramsauer1-4/+10
2022-03-03hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel1-0/+10
2022-03-03hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel1-81/+358
2022-03-03hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel1-53/+238
2022-02-16hw/riscv: virt: Use AIA INTC compatible string when availableAnup Patel1-2/+11
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang1-25/+58
2021-10-28hw/riscv: virt: Use the PLIC config helper functionAlistair Francis1-19/+1
2021-10-28hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis1-1/+1
2021-10-22hw/riscv: virt: Use machine->ram as the system memoryMingwang Li1-4/+2
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel1-1/+112
2021-09-21hw/riscv: virt: Re-factor FDT generationAnup Patel1-200/+327
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel1-5/+9
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel1-1/+1
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis1-1/+1
2021-09-01hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()Peter Maydell1-13/+20
generated by cgit v1.1 at 2025-08-03 10:43:53 +0000