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path: root/hw/riscv/virt.c
AgeCommit message (Expand)AuthorFilesLines
2022-06-10hw/riscv: virt: Generate fw_cfg DT node correctlyAtish Patra1-10/+18
2022-05-24hw/riscv: virt: Fix interrupt parent for dynamic platform devicesAnup Patel1-13/+12
2022-05-24hw/riscv: Make CPU config error handling generous (virt/spike)Tsukasa OI1-1/+1
2022-04-29hw/riscv: Enable TPM backendsAlistair Francis1-0/+4
2022-04-29hw/riscv: virt: Add device plug supportAlistair Francis1-0/+35
2022-04-29hw/riscv: virt: Add support for generating platform FDT entriesAlistair Francis1-0/+19
2022-04-29hw/riscv: virt: Create a platform busAlistair Francis1-19/+49
2022-04-29hw/riscv: virt: Add a machine done notifierAlistair Francis1-90/+101
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng1-1/+1
2022-04-22hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabledNiklas Cassel1-2/+8
2022-04-22hw/riscv: virt: Exit if the user provided -bios in combination with KVMRalf Ramsauer1-4/+10
2022-03-03hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel1-0/+10
2022-03-03hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel1-81/+358
2022-03-03hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel1-53/+238
2022-02-16hw/riscv: virt: Use AIA INTC compatible string when availableAnup Patel1-2/+11
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang1-25/+58
2021-10-28hw/riscv: virt: Use the PLIC config helper functionAlistair Francis1-19/+1
2021-10-28hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis1-1/+1
2021-10-22hw/riscv: virt: Use machine->ram as the system memoryMingwang Li1-4/+2
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel1-1/+112
2021-09-21hw/riscv: virt: Re-factor FDT generationAnup Patel1-200/+327
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel1-5/+9
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel1-1/+1
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis1-1/+1
2021-09-01hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()Peter Maydell1-13/+20
2021-09-01hw/riscv: virt: Move flash node to rootBin Meng1-1/+1
2021-08-26arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell1-1/+0
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng1-4/+2
2021-06-08hw/riscv: Support the official PLIC DT bindingsBin Meng1-1/+5
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng1-1/+5
2021-06-08hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helperBin Meng1-2/+5
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth1-1/+0
2021-03-22hw/riscv: allow ramfb on virtAsherah Connor1-0/+3
2021-03-22hw/riscv: Add fw_cfg support to virtAsherah Connor1-0/+30
2021-03-10hw/riscv: migrate fdt field to generic MachineStateAlex Bennée1-10/+10
2021-03-04hw/riscv: virt: Map high mmio for PCIeBin Meng1-2/+33
2021-03-04hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng1-0/+10
2021-03-04hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng1-7/+7
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng1-6/+3
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis1-4/+4
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis1-4/+5
2020-12-17hw/riscv: virt: Remove compile time XLEN checksAlistair Francis1-15/+17
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis1-1/+1
2020-12-17riscv: virt: Remove target macro conditionalsAlistair Francis1-1/+1
2020-12-15vl: make qemu_get_machine_opts staticPaolo Bonzini1-4/+2
2020-11-03hw/riscv: virt: Allow passing custom DTBAnup Patel1-7/+20
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis1-3/+8
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng1-1/+1
generated by cgit v1.1 at 2024-12-26 02:27:04 +0000