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path: root/hw/riscv/spike.c
AgeCommit message (Expand)AuthorFilesLines
2022-10-17hw/riscv: set machine->fdt in spike_board_init()Daniel Henrique Barboza1-0/+6
2022-09-07hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza1-1/+1
2022-05-24hw/riscv: Make CPU config error handling generous (virt/spike)Tsukasa OI1-1/+1
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng1-1/+1
2022-04-29hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionallyBin Meng1-2/+3
2022-01-21hw/riscv: Remove macros for ELF BIOS image namesAnup Patel1-2/+2
2022-01-21hw/riscv: spike: Allow using binary firmware as biosAnup Patel1-16/+25
2021-10-22hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel1-5/+9
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel1-1/+1
2021-08-26arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell1-1/+0
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng1-4/+2
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng1-1/+5
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth1-1/+0
2021-03-09qtest: delete superfluous inclusions of qtest.hChen Qun1-1/+0
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng1-6/+3
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis1-4/+4
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis1-4/+4
2020-12-17hw/riscv: spike: Remove compile time XLEN checksAlistair Francis1-21/+24
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis1-1/+2
2020-12-17riscv: spike: Remove target macro conditionalsAlistair Francis1-1/+1
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis1-3/+8
2020-09-09hw/riscv: Move riscv_htif model to hw/charBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng1-1/+1
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-1/+2
2020-08-25hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel1-74/+158
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel1-1/+1
2020-08-21hw/riscv: spike: Change the default bios to use generic platform imageBin Meng1-2/+7
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng1-1/+1
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra1-3/+10
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra1-1/+6
2020-07-13riscv: Unify Qemu's reset vector code pathAtish Patra1-38/+3
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster1-2/+2
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster1-4/+3
2020-06-15riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster1-2/+2
2020-06-03hw/riscv: spike: Remove deprecated ISA specific machinesAlistair Francis1-217/+0
2020-04-29hw/riscv/spike: Allow more than one CPUsAnup Patel1-1/+1
2020-04-29hw/riscv/spike: Allow loading firmware separately using -bios optionAnup Patel1-1/+23
2020-04-29hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng1-0/+4
2020-03-03Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...Peter Maydell1-3/+6
2020-02-28hw: Make MachineClass::is_default a boolean typePhilippe Mathieu-Daudé1-1/+1
2020-02-27hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel1-3/+6
2019-11-25hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)1-3/+3
2019-10-28riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng1-2/+0
2019-09-17riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng1-1/+0
2019-08-16Include sysemu/sysemu.h a lot lessMarkus Armbruster1-0/+1
2019-08-16Include hw/hw.h exactly where neededMarkus Armbruster1-1/+0
2019-07-05hw/riscv: Replace global smp variables with machine smp propertiesLike Xu1-0/+3
2019-06-27hw/riscv: Split out the boot functionsAlistair Francis1-17/+4
2019-05-24riscv: spike: Add a generic spike machineAlistair Francis1-1/+105
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