riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-07-19	sifive_u: Fix crash when introspecting the device	Alistair Francis	1	-8/+7
2018-07-05	hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device	Alistair Francis	1	-0/+50
2018-07-05	hw/riscv/sifive_u: Move the uart device tree node under /soc/	Alistair Francis	1	-1/+1
2018-07-05	hw/riscv/sifive_u: Set the interrupt controller number of interrupts	Alistair Francis	1	-1/+1
2018-07-05	hw/riscv/sifive_u: Set the soc device tree node as a simple-bus	Alistair Francis	1	-1/+1
2018-07-05	hw/riscv/sifive_plic: Use gpios instead of irqs	Alistair Francis	1	-2/+3
2018-07-05	hw/riscv/sifive_u: Create a SiFive U SoC object	Alistair Francis	1	-22/+65
2018-05-06	RISC-V: Mark ROM read-only after copying in code	Michael Clark	1	-23/+28
2018-05-06	RISC-V: Remove EM_RISCV ELF_MACHINE indirection	Michael Clark	1	-1/+1
2018-05-06	RISC-V: Remove unused class definitions	Michael Clark	1	-25/+0
2018-05-06	RISC-V: Remove identity_translate from load_elf	Michael Clark	1	-6/+1
2018-05-06	RISC-V: Replace hardcoded constants with enum values	Michael Clark	1	-2/+4
2018-04-26	Change references to serial_hds[] to serial_hd()	Peter Maydell	1	-2/+2
2018-03-07	SiFive Freedom U Series RISC-V Machine	Michael Clark	1	-0/+339