aboutsummaryrefslogtreecommitdiff
path: root/hw/riscv/sifive_u.c
AgeCommit message (Expand)AuthorFilesLines
2023-03-01hw/riscv: Move the dtb load bits outside of create_fdt()Bin Meng1-16/+15
2023-03-01hw/riscv: Skip re-generating DT nodes for a given DTBBin Meng1-0/+1
2023-02-16hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza1-10/+1
2023-02-16hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza1-1/+2
2023-02-07hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza1-1/+2
2023-02-07hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza1-3/+4
2023-01-20hw/riscv/sifive_u.c: simplify create_fdt()Daniel Henrique Barboza1-4/+4
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza1-2/+1
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza1-2/+1
2023-01-20hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()Daniel Henrique Barboza1-6/+5
2023-01-20hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza1-8/+2
2023-01-20hw/riscv/sifive_u: use 'fdt' from MachineStateDaniel Henrique Barboza1-9/+6
2023-01-20hw/riscv/boot.c: introduce riscv_default_firmware_name()Daniel Henrique Barboza1-7/+4
2023-01-06hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"Bin Meng1-1/+2
2022-10-17hw/riscv: set machine->fdt in sifive_u_machine_init()Daniel Henrique Barboza1-0/+3
2022-05-24hw/riscv/sifive_u: Resolve redundant property accessorsBernhard Beschow1-20/+4
2022-05-24hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI1-2/+2
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng1-1/+1
2022-01-08hw/riscv: Use error_fatal for SoC realisationAlistair Francis1-1/+1
2021-12-15hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster1-1/+1
2021-12-15hw/sd/ssi-sd: Do not create SD card within controller's realizeMarkus Armbruster1-1/+12
2021-10-28hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis1-13/+1
2021-10-22hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel1-3/+6
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel1-1/+1
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis1-1/+54
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis1-1/+1
2021-08-26arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell1-1/+0
2021-07-15hw/riscv: sifive_u: Make sure firmware info is 8-byte alignedBin Meng1-2/+3
2021-07-15hw/riscv: sifive_u: Correct the CLINT timebase frequencyBin Meng1-2/+5
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng1-4/+2
2021-06-08hw/riscv: Support the official PLIC DT bindingsBin Meng1-1/+5
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng1-1/+5
2021-06-08hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helperBin Meng1-3/+3
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth1-1/+0
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng1-7/+4
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng1-2/+41
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng1-0/+52
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis1-5/+5
2021-01-16hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng1-5/+1
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis1-5/+5
2020-12-17hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis1-25/+30
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis1-1/+1
2020-12-17hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel1-0/+15
2020-12-15vl: make qemu_get_machine_opts staticPaolo Bonzini1-4/+2
2020-11-03hw/riscv: sifive_u: Allow passing custom DTBAnup Patel1-8/+20
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis1-2/+8
2020-10-22hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis1-5/+13
2020-09-22sifive_u: Register "start-in-flash" as class propertyEduardo Habkost1-8/+8
2020-09-18sifive_u: Rename memmap enum constantsEduardo Habkost1-78/+78
generated by cgit v1.1 at 2024-12-24 01:08:14 +0000