riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-01-16	riscv/sifive_u: fix a memory leak in soc_realize()	Pan Nengyuan	1	-0/+1
2019-11-25	hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()	Zhuang, Siwei (Data61, Kensington NSW)	1	-1/+2
2019-10-28	riscv/sifive_u: Add the start-in-flash property	Alistair Francis	1	-1/+29
2019-10-28	riscv/sifive_u: Manually define the machine	Alistair Francis	1	-13/+31
2019-10-28	riscv/sifive_u: Add QSPI memory region	Alistair Francis	1	-0/+8
2019-10-28	riscv/sifive_u: Add L2-LIM cache memory	Alistair Francis	1	-0/+16
2019-10-28	riscv: sifive_u: Add ethernet0 to the aliases node	Bin Meng	1	-1/+4
2019-10-28	riscv: hw: Drop "clock-frequency" property of cpu nodes	Bin Meng	1	-2/+0
2019-09-17	riscv: sifive_u: Update model and compatible strings in device tree	Bin Meng	1	-2/+3
2019-09-17	riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet	Bin Meng	1	-23/+1
2019-09-17	riscv: sifive_u: Fix broken GEM support	Bin Meng	1	-4/+20
2019-09-17	riscv: sifive_u: Instantiate OTP memory with a serial number	Bin Meng	1	-0/+9
2019-09-17	riscv: sifive_u: Change UART node name in device tree	Bin Meng	1	-1/+1
2019-09-17	riscv: sifive_u: Update UART base addresses and IRQs	Bin Meng	1	-2/+2
2019-09-17	riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes	Bin Meng	1	-3/+4
2019-09-17	riscv: sifive_u: Add PRCI block to the SoC	Bin Meng	1	-1/+23
2019-09-17	riscv: sifive_u: Generate hfclk and rtcclk nodes	Bin Meng	1	-0/+23
2019-09-17	riscv: sifive_u: Update PLIC hart topology configuration string	Bin Meng	1	-3/+4
2019-09-17	riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC	Bin Meng	1	-25/+67
2019-09-17	riscv: sifive_u: Set the minimum number of cpus to 2	Bin Meng	1	-1/+4
2019-09-17	riscv: sifive_u: Remove the unnecessary include of prci header	Bin Meng	1	-1/+0
2019-09-17	riscv: hw: Change create_fdt() to return void	Bin Meng	1	-7/+4
2019-09-17	riscv: hw: Remove not needed PLIC properties in device tree	Bin Meng	1	-2/+0
2019-09-17	riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell	Bin Meng	1	-9/+9
2019-09-17	riscv: hw: Remove superfluous "linux, phandle" property	Bin Meng	1	-4/+0
2019-09-17	riscv: sifive_u: Fix clock-names property for ethernet node	Guenter Roeck	1	-1/+1
2019-09-17	riscv: sivive_u: Add dummy serial clock and aliases entry for uart	Guenter Roeck	1	-2/+17
2019-09-17	riscv: sifive_u: Add support for loading initrd	Guenter Roeck	1	-3/+17
2019-08-16	Include sysemu/sysemu.h a lot less	Markus Armbruster	1	-0/+1
2019-08-16	Include hw/hw.h exactly where needed	Markus Armbruster	1	-1/+0
2019-07-18	hw/riscv: Load OpenSBI as the default firmware	Alistair Francis	1	-3/+4
2019-07-05	hw/riscv: Replace global smp variables with machine smp properties	Like Xu	1	-4/+7
2019-06-27	hw/riscv: Add support for loading a firmware	Alistair Francis	1	-0/+4
2019-06-27	hw/riscv: Split out the boot functions	Alistair Francis	1	-15/+2
2019-06-27	riscv: sifive_u: Update the plic hart config to support multicore	Bin Meng	1	-1/+15
2019-06-27	riscv: sifive_u: Do not create hard-coded phandles in DT	Bin Meng	1	-7/+10
2019-03-19	riscv: sifive_u: Correct UART0's IRQ in the device tree	Bin Meng	1	-1/+1
2019-03-19	riscv: sifive_u: Allow up to 4 CPUs to be created	Alistair Francis	1	-1/+4
2019-02-11	riscv: Ensure the kernel start address is correctly cast	Alistair Francis	1	-1/+1
2019-02-05	elf: Add optional function ptr to load_elf() to parse ELF notes	Liam Merwick	1	-1/+1
2018-12-20	RISC-V: Enable second UART on sifive_e and sifive_u	Michael Clark	1	-3/+2
2018-12-20	sifive_u: Set 'clock-frequency' DT property for SiFive UART	Anup Patel	1	-0/+2
2018-12-20	sifive_u: Add clock DT node for GEM ethernet	Anup Patel	1	-1/+17
2018-10-17	RISC-V: Don't add NULL bootargs to device-tree	Michael Clark	1	-1/+3
2018-09-24	Drop "qemu:" prefix from error_report() arguments	Mao Zhongyi	1	-1/+1
2018-07-19	sifive_u: Fix crash when introspecting the device	Alistair Francis	1	-8/+7
2018-07-05	hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device	Alistair Francis	1	-0/+50
2018-07-05	hw/riscv/sifive_u: Move the uart device tree node under /soc/	Alistair Francis	1	-1/+1
2018-07-05	hw/riscv/sifive_u: Set the interrupt controller number of interrupts	Alistair Francis	1	-1/+1
2018-07-05	hw/riscv/sifive_u: Set the soc device tree node as a simple-bus	Alistair Francis	1	-1/+1