riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-02-16	hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()	Daniel Henrique Barboza	1	-1/+2
2023-02-16	hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()	Daniel Henrique Barboza	1	-1/+2
2023-02-07	include/hw/riscv/opentitan: update opentitan IRQs	Wilfred Mallawa	1	-40/+40
2023-01-20	hw/riscv/boot.c: use MachineState in riscv_load_kernel()	Daniel Henrique Barboza	1	-2/+1
2023-01-06	hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization	Bin Meng	1	-2/+0
2023-01-06	hw/riscv/opentitan: add aon_timer base unimpl	Wilfred Mallawa	1	-0/+3
2023-01-06	hw/riscv/opentitan: bump opentitan	Wilfred Mallawa	1	-8/+13
2022-09-27	hw/riscv: opentitan: Expose the resetvec as a SoC property	Alistair Francis	1	-1/+7
2022-09-27	hw/riscv: opentitan: Fixup resetvec	Alistair Francis	1	-1/+1
2022-09-07	hw/riscv: opentitan: bump opentitan version	Wilfred Mallawa	1	-4/+8
2022-05-24	hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)	Tsukasa OI	1	-1/+1
2022-04-22	riscv: opentitan: Connect opentitan SPI Host	Wilfred Mallawa	1	-4/+32
2022-03-03	hw: riscv: opentitan: fixup SPI addresses	Wilfred Mallawa	1	-3/+9
2022-01-21	riscv: opentitan: fixup plic stride len	Wilfred Mallawa	1	-1/+1
2022-01-08	hw/riscv: Use error_fatal for SoC realisation	Alistair Francis	1	-1/+1
2021-10-28	hw/riscv: opentitan: Fixup the PLIC context addresses	Alistair Francis	1	-2/+2
2021-10-22	hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id	Bin Meng	1	-4/+12
2021-10-22	hw/riscv: opentitan: Update to the latest build	Alistair Francis	1	-5/+17
2021-09-21	hw/riscv: opentitan: Correct the USB Dev address	Alistair Francis	1	-1/+1
2021-09-21	hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines	Alistair Francis	1	-0/+3
2021-09-21	hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines	Alistair Francis	1	-0/+8
2021-07-15	hw/riscv: opentitan: Add the flash alias	Alistair Francis	1	-0/+6
2021-07-15	hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri	Alistair Francis	1	-0/+3
2021-06-24	hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer	Alistair Francis	1	-3/+11
2021-05-11	hw/riscv: Fix OT IBEX reset vector	Alexander Wagner	1	-1/+1
2021-05-11	hw/opentitan: Update the interrupt layout	Alistair Francis	1	-4/+4
2021-05-02	Do not include exec/address-spaces.h if it's not really necessary	Thomas Huth	1	-1/+0
2021-03-04	hw/riscv: Drop 'struct MemmapEntry'	Bin Meng	1	-6/+3
2020-12-17	riscv/opentitan: Update the OpenTitan memory layout	Alistair Francis	1	-24/+57
2020-10-22	hw/riscv: Load the kernel after the firmware	Alistair Francis	1	-1/+2
2020-09-09	target/riscv: cpu: Set reset vector based on the configured property value	Bin Meng	1	-0/+1
2020-08-27	opentitan: Rename memmap enum constants	Eduardo Habkost	1	-42/+42
2020-07-10	error: Eliminate error_propagate() with Coccinelle, part 1	Markus Armbruster	1	-5/+2
2020-07-10	qom: Put name parameter before value / visitor parameter	Markus Armbruster	1	-2/+2
2020-07-10	qdev: Use returned bool to check for qdev_realize() etc. failure	Markus Armbruster	1	-4/+2
2020-06-19	hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions	Bin Meng	1	-15/+14
2020-06-19	riscv/opentitan: Connect the UART device	Alistair Francis	1	-2/+23
2020-06-19	riscv/opentitan: Connect the PLIC device	Alistair Francis	1	-2/+12
2020-06-19	riscv/opentitan: Fix the ROM size	Alistair Francis	1	-1/+2
2020-06-15	qdev: Convert bus-less devices to qdev_realize() with Coccinelle	Markus Armbruster	1	-2/+1
2020-06-15	sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2	Markus Armbruster	1	-4/+2
2020-06-15	qom: Less verbose object_initialize_child()	Markus Armbruster	1	-2/+1
2020-06-15	riscv: Fix to put "riscv.hart_array" devices on sysbus	Markus Armbruster	1	-3/+2
2020-06-03	riscv: Initial commit of OpenTitan machine	Alistair Francis	1	-0/+184