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path: root/hw/riscv/microchip_pfsoc.c
AgeCommit message (Expand)AuthorFilesLines
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza1-2/+1
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza1-2/+1
2023-01-20hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza1-8/+2
2023-01-06hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley1-0/+6
2023-01-06hw/riscv: pfsoc: add missing FICs as unimplementedConor Dooley1-52/+63
2022-09-07hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripheralsConor Dooley1-6/+61
2022-09-07hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza1-1/+1
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng1-1/+1
2022-01-08hw/riscv: Use error_fatal for SoC realisationAlistair Francis1-1/+1
2021-12-15hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster1-1/+1
2021-10-28hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis1-13/+1
2021-10-22hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ra...Bin Meng1-16/+20
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel1-3/+6
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel1-1/+1
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis1-1/+1
2021-06-08hw/riscv: microchip_pfsoc: Support direct kernel bootBin Meng1-3/+78
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth1-1/+0
2021-05-02hw: Do not include hw/irq.h if it is not necessaryThomas Huth1-1/+0
2021-03-22hw/riscv: microchip_pfsoc: Map EMMC/SD mux registerBin Meng1-0/+6
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng1-6/+3
2020-12-17hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool1-0/+21
2020-11-03hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng1-0/+6
2020-11-03hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng1-6/+44
2020-11-03hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng1-1/+10
2020-11-03hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng1-3/+6
2020-11-03hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng1-5/+8
2020-11-03hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng1-0/+18
2020-11-03hw/riscv: microchip_pfsoc: Document where to look at the SoC memory mapsBin Meng1-0/+18
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng1-1/+1
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-1/+5
2020-09-09hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng1-0/+14
2020-09-09hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng1-0/+39
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng1-0/+15
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng1-0/+23
2020-09-09hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng1-0/+30
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng1-0/+312
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