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path: root/hw/riscv/boot.c
AgeCommit message (Expand)AuthorFilesLines
2023-02-16hw/riscv/boot.c: make riscv_load_initrd() staticDaniel Henrique Barboza1-40/+40
2023-02-16hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza1-0/+11
2023-02-16hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza1-3/+17
2023-02-07hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza1-12/+23
2023-02-07hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza1-5/+25
2023-02-07hw/riscv/boot.c: calculate fdt size after fdt_pack()Daniel Henrique Barboza1-4/+6
2023-02-07hw/riscv: boot: Don't use CSRs if they are disabledAlistair Francis1-0/+9
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza1-1/+2
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza1-2/+4
2023-01-20hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza1-6/+12
2023-01-20hw/riscv/boot.c: exit early if filename is NULL in load functionsDaniel Henrique Barboza1-0/+6
2023-01-20hw/riscv/boot.c: Introduce riscv_find_firmware()Bin Meng1-14/+25
2023-01-20hw/riscv/boot.c: introduce riscv_default_firmware_name()Daniel Henrique Barboza1-0/+9
2023-01-20hw/riscv/boot.c: make riscv_find_firmware() staticDaniel Henrique Barboza1-22/+22
2022-10-27riscv: re-randomize rng-seed on rebootJason A. Donenfeld1-0/+3
2022-10-14hw/riscv: virt: Enable booting S-mode firmware from pflashSunil V L1-0/+29
2022-10-14hw/riscv: Update comment for qtest check in riscv_find_firmware()Bin Meng1-2/+2
2022-09-07hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza1-3/+1
2022-07-03hw/riscv: boot: Reduce FDT address alignment constraintsAlistair Francis1-2/+2
2022-06-10hw/core/loader: return image sizes as ssize_tJamie Iles1-2/+3
2022-04-22hw/riscv: boot: Support 64bit fdt address.Dylan Jhong1-5/+7
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau1-1/+0
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang1-1/+15
2021-12-20hw/riscv: Use load address rather than entry point for fw_dynamic next_addrJessica Clarke1-3/+10
2021-10-28hw/riscv: boot: Add a PLIC config string functionAlistair Francis1-0/+25
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson1-1/+1
2021-07-15hw/riscv/boot: Check the error of fdt_pack()Alistair Francis1-2/+4
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis1-6/+4
2021-01-16RISC-V: Place DTB at 3GB boundary instead of 4GBAtish Patra1-4/+4
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis1-21/+10
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis1-25/+30
2020-12-17hw/riscv: Expand the is 32-bit check to support more CPUsAlistair Francis1-1/+11
2020-12-10vl: extract softmmu/datadir.cPaolo Bonzini1-0/+1
2020-12-10riscv: do not use ram_size globalPaolo Bonzini1-2/+3
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis1-5/+14
2020-10-22hw/riscv: Add a riscv_is_32_bit() functionAlistair Francis1-0/+9
2020-10-22hw/riscv: Return the end address of the loaded firmwareAlistair Francis1-11/+17
2020-09-25load_elf: Remove unused address variables from callersBALATON Zoltan1-4/+4
2020-07-13RISC-V: Support 64 bit start addressAtish Patra1-1/+5
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra1-4/+38
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra1-15/+38
2020-07-13riscv: Unify Qemu's reset vector code pathAtish Patra1-0/+46
2020-06-03riscv: Change the default behavior if no -bios option is specifiedBin Meng1-27/+4
2020-06-03riscv: Suppress the error report for QEMU testing with riscv_find_firmware()Bin Meng1-3/+11
2020-04-29hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel1-5/+8
2020-01-29hw/core/loader: Let load_elf() populate a field with CPU-specific flagsAleksandar Markovic1-2/+2
2019-11-25hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)1-3/+4
2019-10-28riscv/boot: Fix possible memory leakAlistair Francis1-7/+4
2019-09-17riscv: Resolve full path of the given bios imageBin Meng1-3/+3
2019-09-17riscv: Add a helper routine for finding firmwareBin Meng1-7/+15