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path: root/hw/riscv/Kconfig
AgeCommit message (Expand)AuthorFilesLines
2023-03-06hw/riscv/virt: Enable basic ACPI infrastructureSunil V L1-0/+1
2023-01-06hw/riscv: Sort machines Kconfig options in alphabetical orderBin Meng1-7/+9
2023-01-06hw/riscv: Fix opentitan dependency to SIFIVE_PLICBin Meng1-0/+1
2023-01-06hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLICBin Meng1-5/+0
2022-04-29hw/riscv: Enable TPM backendsAlistair Francis1-0/+1
2022-04-29hw/riscv: virt: Create a platform busAlistair Francis1-0/+1
2022-03-03hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel1-0/+1
2022-03-03hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel1-0/+1
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel1-6/+6
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis1-0/+1
2021-09-01hw/char: Add config for shakti uartVijai Kumar K1-4/+1
2021-07-20hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machinesPhilippe Mathieu-Daudé1-0/+5
2021-05-11hw/riscv: Enable VIRTIO_VGA for RISC-V virt machineAlistair Francis1-0/+1
2021-05-11riscv: Add initial support for Shakti C machineVijai Kumar K1-0/+10
2021-03-22hw/riscv: Add fw_cfg support to virtAsherah Connor1-0/+1
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng1-0/+1
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng1-0/+2
2020-11-03hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng1-0/+1
2020-11-03hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng1-0/+1
2020-11-03hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng1-0/+1
2020-09-09hw/riscv: Sort the Kconfig options in alphabetical orderBin Meng1-29/+29
2020-09-09hw/riscv: Drop CONFIG_SIFIVEBin Meng1-9/+5
2020-09-09hw/riscv: Always build riscv_hart.cBin Meng1-9/+0
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng1-0/+1
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng1-0/+2
2020-09-09hw/riscv: Move riscv_htif model to hw/charBin Meng1-3/+0
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng1-0/+5
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng1-0/+5
2020-09-09hw/riscv: Move sifive_gpio model to hw/gpioBin Meng1-0/+2
2020-09-09hw/riscv: Move sifive_u_otp model to hw/miscBin Meng1-0/+1
2020-09-09hw/riscv: Move sifive_u_prci model to hw/miscBin Meng1-0/+1
2020-09-09hw/riscv: Move sifive_e_prci model to hw/miscBin Meng1-0/+1
2020-09-09hw/riscv: sifive_u: Connect a DMA controllerBin Meng1-0/+1
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng1-0/+1
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng1-0/+1
2020-09-09hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng1-0/+1
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng1-0/+6
2020-06-19hw/char: Initial commit of Ibex UARTAlistair Francis1-0/+4
2020-06-03riscv: Initial commit of OpenTitan machineAlistair Francis1-0/+5
2020-02-10riscv: virt: Use Goldfish RTC deviceAnup Patel1-0/+1
2019-10-28riscv/virt: Add the PFlash CFI01 deviceAlistair Francis1-0/+1
2019-09-17riscv: sifive_u: Fix broken GEM supportBin Meng1-0/+1
2019-09-17riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng1-0/+1
2019-03-18kconfig: add CONFIG_MSI_NONBROKENPaolo Bonzini1-0/+1
2019-03-11riscv/Kconfig: enable PCI_DEVICESDavid Abdurachmanov1-0/+3
2019-03-07riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directivesPaolo Bonzini1-0/+13
2019-03-07kconfig: introduce kconfig filesPaolo Bonzini1-0/+20
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