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path: root/hw/ppce500_pci.c
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2012-12-19misc: move include files to include/qemu/Paolo Bonzini1-1/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-1/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-17Merge commit '1dd3a74d2ee2d873cde0b390b536e45420b3fe05' into HEADPaolo Bonzini1-2/+2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-17pci: update all users to look in pci/Michael S. Tsirkin1-2/+2
update all users so we can remove the makefile hack. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2012-12-14PPC: e500: pci: Export slot2irq calculationAlexander Graf1-1/+2
We need the calculation method to get from a PCI slot ID to its respective interrupt line twice. Once in the internal map function and once when assembling the device tree. So let's extract the calculation to a separate function that can be called by both users. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14PPC: E500: PCI: Make IRQ calculation more genericAlexander Graf1-10/+3
The IRQ line calculation is more or less hardcoded today. Instead, let's write it as an algorithmic function that theoretically allows an arbitrary number of PCI slots. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14PPC: E500: PCI: Make first slot qdev settableAlexander Graf1-1/+8
Today the first slot id in our e500 pci implementation is hardcoded to 0x11. Keep it there as default, but allow users to change the default to a different id. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14PPC: e500: Declare pci bridge as bridgeAlexander Graf1-0/+6
The new PCI host bridge device needs to identify itself as PCI host bridge. Declare it as such. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14Adding BAR0 for e500 PCI controllerBharat Bhushan1-1/+28
PCI Root complex have TYPE-1 configuration header while PCI endpoint have type-0 configuration header. The type-1 configuration header have a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci address space to CCSR address space. This can used for 2 purposes: 1) for MSI interrupt generation 2) Allow CCSR registers access when configured as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest. What I observed is that when guest read the size of BAR0 of host controller configuration header (TYPE1 header) then it always reads it as 0. When looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller device registering BAR0. I do not find any other controller also doing so may they do not use BAR0. There are two issues when BAR0 is not there (which I can think of): 1) There should be BAR0 emulated for PCI Root complex (TYPE1 header) and when reading the size of BAR0, it should give size as per real h/w. 2) Do we need this BAR0 inbound address translation? When BAR0 is of non-zero size then it will be configured for PCI address space to local address(CCSR) space translation on inbound access. The primary use case is for MSI interrupt generation. The device is configured with an address offsets in PCI address space, which will be translated to MSI interrupt generation MPIC registers. Currently I do not understand the MSI interrupt generation mechanism in QEMU and also IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines. But this BAR0 will be used when using MSI on e500. I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c, but i do not see these being used for address translation. So far that works because pci address space and local address space are 1:1 mapped. BAR0 inbound translation + ATMU translation will complete the address translation of inbound traffic. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> [agraf: fix double variable assignment w/o read] Signed-off-by: Alexander Graf <agraf@suse.de>
2012-10-29PPC: e500: Map PIO space into core memory regionAlexander Graf1-2/+7
On PPC, we don't have PIO. So usually PIO space behind a PCI bridge is accessible via MMIO. Do this mapping explicitly by mapping the PIO space of our PCI bus into a memory region that lives in memory space. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity1-2/+2
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-08-22pci: Tidy up PCI host bridgesAndreas Färber1-1/+1
Adopt the QOM parent field name and enforce QOM-style access via casts. Don't just typedef PCIHostState, either use it directly or embed it. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-08-22pci: Derive PCI host bridges from TYPE_PCI_HOST_BRIDGEAndreas Färber1-2/+2
Use PCIHostState and PCI_HOST_BRIDGE() where appropriate. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-08-22ppce500_pci: QOM'ify e500 PCI host bridgeAndreas Färber1-5/+11
Introduce type constant and cast macro. Avoid accessing parent fields directly. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-08-22pci: Make host bridge TypeInfos constAndreas Färber1-2/+2
During the QOM migration they were amended with further info but this is no longer the case. All static TypeInfos can be const these days. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-15qom: Unify type registrationAndreas Färber1-2/+3
Replace device_init() with generalized type_init(). While at it, unify naming convention: type_init([$prefix_]register_types) Also, type_init() is a function, so add preceding blank line where necessary and don't put a semicolon after the closing brace. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Anthony Liguori <anthony@codemonkey.ws> Cc: malc <av1474@comtv.ru> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-03qdev: register all types natively through QEMU Object ModelAnthony Liguori1-12/+16
This was done in a mostly automated fashion. I did it in three steps and then rebased it into a single step which avoids repeatedly touching every file in the tree. The first step was a sed-based addition of the parent type to the subclass registration functions. The second step was another sed-based removal of subclass registration functions while also adding virtual functions from the base class into a class_init function as appropriate. Finally, a python script was used to convert the DeviceInfo structures and qdev_register_subclass functions to TypeInfo structures, class_init functions, and type_register_static calls. We are almost fully converted to QOM after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-01-27sysbus: apic: ioapic: convert to QEMU Object ModelAnthony Liguori1-5/+12
This converts three devices because apic and ioapic are subclasses of sysbus. Converting subclasses independently of their base class is prohibitively hard. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-01-27pci: convert to QEMU Object ModelAnthony Liguori1-7/+14
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-12-19ppce500_pci: remove sysbus_init_mmio_cb2 usageBenoît Canet1-21/+6
Expose only one container MemoryRegion to sysbus. (Peter Maydell's idea) Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Benoît Canet <benoit.canet@gmail.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-11-24ppce500_pci: convert to memory APIAvi Kivity1-20/+14
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-30ppc/e500_pci: Fix an array overflow issueLiu Yu-B132011-16/+22
When access PPCE500_PCI_IW1 the previous index get overflow. The patch fix the issue and update all to keep consistent style. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30ppc/e500_pci: Fix code styleLiu Yu-B132011-20/+56
Put trailing statements on next line. Signed-off-by: Liu Yu <yu.liu@freescale.com> Reviewed-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-09-04pci_host: convert conf index and data ports to memory APIAvi Kivity1-11/+10
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-08-25Revert "Merge remote-tracking branch 'qemu-kvm/memory/batch' into staging"Anthony Liguori1-10/+11
This reverts commit 8ef9ea85a2cc1007eaefa53e6871f1f83bcef22d, reversing changes made to 444dc48298c480e42e15a8fe676be737d8a6b2a1. From Avi: Please revert the entire pull (git revert 8ef9ea85a2cc1) while I work this out - it isn't trivial. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-24pci_host: convert conf index and data ports to memory APIAvi Kivity1-11/+10
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-08-22ppce500_pci: convert to sysbus_init_mmio_cb2()Avi Kivity1-1/+11
Not a huge step forward, but at least we now have a 1:1 relationship between registration and unregistration. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-08pci: pass I/O address space to new PCI busAvi Kivity1-3/+4
This lets us register BARs in the I/O address space. Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-07-29pci: pass address space to pci bus when createdAvi Kivity1-1/+5
This is now done sloppily, via get_system_memory(). Eventually callers will be converted to stop using that. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-06-15ppce500: move device/vendor/class id to qdevMichael S. Tsirkin1-10/+3
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2011-05-12PPC: Qdev'ify e500 pciAlexander Graf1-60/+76
The e500 PCI controller isn't qdev'ified yet. This leads to severe issues when running with -drive. To be able to use a virtio disk with an e500 VM, let's convert the PCI controller over to qdev. Reviewed-by: Paul Brook <paul@codesourcery.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-22vmstate: port ppce500_pciJuan Quintela1-47/+40
Signed-off-by: Juan Quintela <quintela@redhat.com>
2011-04-09mpc85xx_pci_map_irq: change "unknow" to "unknown"Scott Wood1-1/+1
Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2010-12-11pci-host: Delegate bswap to mmio layerAlexander Graf1-2/+4
The only reason we have bswap versions of the pci host code is that most pci host devices are little endian. The ppc e500 is the only odd one here, being big endian. So let's directly pass the endianness down to the mmio layer and not worry about it on the pci host layer. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-12-11Add endianness as io mem parameterAlexander Graf1-1/+2
As stated before, devices can be little, big or native endian. The target endianness is not of their concern, so we need to push things down a level. This patch adds a parameter to cpu_register_io_memory that allows a device to choose its endianness. For now, all devices simply choose native endian, because that's the same behavior as before. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-09-08Revert "PPC: Qdev'ify e500 pci"Anthony Liguori1-73/+33
This reverts commit 13b7fdeffa68e3382231a70308593ae6a75d96c3. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-09-08Revert "PPC: Make e500 pci byte swap config data"Anthony Liguori1-1/+1
This reverts commit cfb207e643d94e3e96d456b1df14c5e36f6aa9e5. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-09-05PPC: Make e500 pci byte swap config dataAlexander Graf1-1/+1
The config data field on the e500 pci controller is in little endian, so we need to enable byte swap there. Signed-off-by: Alexander Graf <agraf@suse.de>
2010-09-05PPC: Qdev'ify e500 pciAlexander Graf1-33/+73
The e500 PCI controller isn't qdev'ified yet. This leads to severe issues when running with -drive. To be able to use a virtio disk with an e500 VM, let's convert the PCI controller over to qdev. Signed-off-by: Alexander Graf <agraf@suse.de>
2010-07-11pci: use PCI_DEVFN() where appropriate.Isaku Yamahata1-1/+2
Use PCI_DEVFN() and PCI_FUNC_MAX where appropriate. This patch make it clear that func = 0. test: The following object files with/without this patch are stripped and compared. They remains same. arm-softmmu/versatile_pci.o libhw32/ppce500_pci.o libhw32/unin_pci.o libhw64/ppce500_pci.o libhw64/unin_pci.o mips-softmmu/gt64xxx.o mips64-softmmu/gt64xxx.o mips64el-softmmu/gt64xxx.o mipsel-softmmu/gt64xxx.o Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yu Liu <yu.liu@freescale.com> Cc: Paul Brook <paul@codesourcery.com> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-06savevm: Add DeviceState paramAlex Williamson1-2/+2
When available, we'd like to be able to access the DeviceState when registering a savevm. For buses with a get_dev_path() function, this will allow us to create more unique savevm id strings. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-03-30Compile most PPC devices only onceBlue Swirl1-2/+0
Make byte swapping unconditional since PPC is big endian. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-21Compile pci_host only onceBlue Swirl1-2/+2
Convert pci_host_conf_register_mmio_noswap(x) to pci_host_conf_register_mmio(x, 0). Convert pci_host_conf_register_mmio(x) to pci_host_conf_register_mmio(x, 1) for big endian hosts, all cases happen to be BE. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-01pci: shorten pci_host_{conf, data}_register_xxx function a bit.Isaku Yamahata1-2/+2
pci_host_data_register_io_memory and its variants are too long a bit. So shorten them. Now they are pci_host_{conf, data}_register_{mmio, mmio_noswap, ioport}() Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-11-09pci_host: consolidate pci config address access.Isaku Yamahata1-33/+1
consolidate pci_config address access into pci_host.c Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-11-09pci_host.h: move functions in pci_host.h into .c file.Isaku Yamahata1-16/+1
split static functions in pci_host.h into pci_host.c and pci_host_template.h. Later a structures declared in pci_host.h, PCIHostState, will be used. However pci_host.h doesn't allow to include itself easily. This patches addresses it. pci_host.h includes functions which are instantiated in .c by including pci_host.h with typedefing pci_addr_t. pci_addr_t is per pci host bridge and is typedef'ed to uint32_t for ioio or target_phys_addr_t for mmio in .c file. That prevents from including pci_host.h to use PCIHostState because of requiring type, pci_addr_t. Its purpose to include is to instantiate io function for mmio or ioio depending on which pci host bridge requires ioio or mmio. To avoid including code, we always instantiate both version. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-6/+6
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc1-6/+6
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-09-04We want the argument pass to set_irq to be opaqueJuan Quintela1-1/+3
piix_pci want to pass more things that the pic Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-25Make CPURead/WriteFunc structure 'const'Blue Swirl1-6/+6
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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