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2013-07-29pc: replace i440fx_common_init() with i440fx_init()Igor Mammedov1-37/+13
It isn't used anywhere else. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1375109277-25561-4-git-send-email-imammedo@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pc: add I440FX QOM cast macroIgor Mammedov1-2/+6
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1375109277-25561-3-git-send-email-imammedo@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pci-bridge: Turn PCIBridge into abstract QOM typeAndreas Färber1-4/+3
Introduce TYPE_PCI_BRIDGE as base type and use PCI_BRIDGE() casts. Reviewed-by: Don Koch <dkoch@verizon.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> [AF: Updated pbm-bridge parent to TYPE_PCI_BRIDGE] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29devices: Associate devices to their logical categoryMarcel Apfelbaum4-0/+6
The category will be used to sort the devices displayed in the command line help. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Message-id: 1375107465-25767-4-git-send-email-marcel.a@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25sparc64: unbreakPaolo Bonzini1-19/+28
... by making apb a subclass of TYPE_PCI_HOST_BRIDGE. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-21-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25sparc64: remove indirection for I/O port accessPaolo Bonzini1-52/+2
This fixes endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-13-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25mips_fulong2e: do not use isa_mmioPaolo Bonzini1-15/+10
This board is little-endian, but still isa_mmio should die. :) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-12-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-23q35: Use QOM realize for q35 host bridgeHu Tao1-14/+15
And split off MemoryRegion initialization into instance_init. Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23q35: Use type-safe cast instead of direct access of parent devHu Tao1-21/+22
And remove variables if possible. Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> [AF: Converted remaining access and renamed to parent_obj] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23i440fx-pcihost: Use QOM realize for i440fx-pcihostHu Tao1-12/+17
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23i440fx: Use type-safe cast instead of direct access of parent devHu Tao1-9/+16
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> [AF: Converted remaining accesses and renamed to parent_obj] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-08Merge remote-tracking branch 'mst/tags/for_anthony' into stagingAnthony Liguori2-0/+26
pci,misc enhancements This includes some pci enhancements: Better support for systems with multiple PCI root buses FW cfg interface for more robust pci programming in BIOS Minor fixes/cleanups for fw cfg and cross-version migration - because of dependencies with other patches Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 07 Jul 2013 03:11:18 PM CDT using RSA key ID D28D5469 # gpg: Can't check signature: public key not found # By David Gibson (10) and others # Via Michael S. Tsirkin * mst/tags/for_anthony: pci: Fold host_buses list into PCIHostState functionality pci: Remove domain from PCIHostBus pci: Simpler implementation of primary PCI bus pci: Add root bus parameter to pci_nic_init() pci: Add root bus argument to pci_get_bus_devfn() pci: Replace pci_find_domain() with more general pci_root_bus_path() pci: Use helper to find device's root bus in pci_find_domain() pci: Abolish pci_find_root_bus() pci: Move pci_read_devaddr to pci-hotplug-old.c pci: Cleanup configuration for pci-hotplug.c pvpanic: fix fwcfg for big endian hosts pvpanic: initialization cleanup MAINTAINERS: s/Marcelo/Paolo/ e1000: cleanup process_tx_desc pc_piix: cleanup init compat handling pc: pass PCI hole ranges to Guests pci: store PCI hole ranges in guestinfo structure range: add Range structure Message-id: 1373228271-31223-1-git-send-email-mst@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-07pci: Replace pci_find_domain() with more general pci_root_bus_path()David Gibson2-0/+18
pci_find_domain() is used in a number of places where we want an id for a whole PCI domain (i.e. the subtree under a PCI root bus). The trouble is that many platforms may support multiple independent host bridges with no hardware supplied notion of domain number. This patch, therefore, replaces calls to pci_find_domain() with calls to a new pci_root_bus_path() returning a string. The new call is implemented in terms of a new callback in the host bridge class, so it can be defined in some way that's well defined for the platform. When no callback is available we fall back on the qbus name. Most current uses of pci_find_domain() are for error or informational messages, so the change in identifiers should be harmless. The exception is pci_get_dev_path(), whose results form part of migration streams. To maintain compatibility with old migration streams, the PIIX PCI host is altered to always supply "0000" for this path, which matches the old domain number (since the code didn't actually support domains other than 0). For the pseries (spapr) PCI bridge we use a different platform-unique identifier (pseries machines can routinely have dozens of PCI host bridges). Theoretically that breaks migration streams, but given that we don't yet have migration support for pseries, it doesn't matter. Any other machines that have working migration support including PCI devices will need to be updated to maintain migration stream compatibility. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-07-04hw/p*: pass owner to memory_region_init* functionsPaolo Bonzini9-56/+57
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-04pam: pass device to init_pam and use it to set ownerPaolo Bonzini3-11/+13
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-04memory: add owner argument to initialization functionsPaolo Bonzini10-57/+57
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-04pci: store PCI hole ranges in guestinfo structureMichael S. Tsirkin1-0/+8
Will be used to pass hole ranges to guests. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-06-02dec.c - move to pci-bridgeMichael S. Tsirkin3-167/+0
Looks like dec.c is in pci-host by mistake. Moving it over to pci-bridge. Acked-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-05-30q35: set fw_nameMichael S. Tsirkin1-0/+1
PCI host bridges need to set fw_name to be discoverable by bios for boot device selection. In particular, seabios expects root device to be called "/pci/@i0cf8", so let's set it up like that for Q35. Cc: qemu-stable@nongnu.org Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Amos Kong <akong@redhat.com>
2013-05-15hw/pci-host/versatile.c: Provide property for forcing broken IRQ mappingPeter Maydell1-1/+13
Although we try our best to automatically detect broken versions of Linux which assume the old broken IRQ mapping we used to implement for our model of the Versatile PCI controller, it turns out that some particularly new kernels manage to outwit the autodetection. We therefore provide a property for enabling the old broken IRQ mapping, so that if users happen to have such a kernel they can work around its deficiencies with the command line option: -global versatile_pci.broken-irq-mapping=1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1368545616-22344-4-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-05-15hw/pci-host/versatile.c: Update autodetect to detect newer kernelsPeter Maydell1-7/+62
Newer versatilepb kernels still don't get the IRQ mapping right for the PCI controller, but they get it differently wrong (they add a fixed +64 offset to everything they write to PCI_INTERRUPT_LINE). Update the autodetection to handle these too, and include a more detailed comment on the various different behaviours that might be present. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1368545616-22344-3-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-05-15Revert "versatile_pci: Put the host bridge PCI device at slot 29"Peter Maydell1-2/+0
This reverts commit 5f37ef92b7690423ac6311d3c597e182fc5f8fe6. It turns out that some kernels incorrectly depend on the old QEMU behaviour of not putting the host PCI bridge device where the hardware puts it, because they use a swizzling IRQ mapping which is incorrect but happens to match up with old broken QEMU when the slot number mod 4 is zero. Since we start PCI devices at 11, if we put the host bridge at 29 then the first real PCI device goes at 11 and doesn't work. Not putting the host bridge at 29 means it defaults to 11, so the first real PCI device is at 12 and works. Since continuing with the old behaviour doesn't cause problems for kernels which do work with hardware, the simplest fix for this is to revert the change. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1368545616-22344-2-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-27sparc64: use direct interrupt mapping for PCI devicesArtyom Tarasenko1-1/+1
Every PCI Slot in PBM has 4 directly mapped IRQ lines. Use the IRQ routing schema 0bssnn (Bus, Slot, interrupt Number) described in Section 19.3.3 of UltraSPARC™-IIi User's Manual. Please note that this patch requires the OpenBIOS counterpart patch. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-04-27sparc64: fix loosing interruptsArtyom Tarasenko1-18/+96
- clear interrupts only on writing to the interrupt clear registers - don't overwrite a currently active interrupt request - use the correct addresses for the interrupt clear registers (section 19.3.3.3 of the UltraSPARC™-IIi User’s Manual) Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-04-27sparc64: allow 64 IRQ linesArtyom Tarasenko1-1/+1
According to UltraSPARC™-IIi User’s Manual, PBM has 64 IRQ lines. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-04-19hw/versatile_pci: Drop unnecessary vpb_pci_config_addr()Peter Maydell1-7/+2
Drop the vpb_pci_config_addr() function -- it is unnecessary since the size of the memory regions means the hwaddr is always within the 24 bit size. (This function was probably a leftover from when read/write functions were called with absolute addresses rather than relative ones.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paul Brook <paul@codesourcery.com>
2013-04-19versatile_pci: Expose PCI memory space to systemPeter Maydell1-1/+71
The VersatilePB's PCI controller exposes the PCI memory space to the system via three regions controlled by the mapping control registers. Implement this so that guests can actually use MMIO-BAR PCI cards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paul Brook <paul@codesourcery.com>
2013-04-19versatile_pci: Implement the PCI controller's control registersPeter Maydell1-5/+122
The versatile_pci PCI controller has a set of control registers which handle the mapping between PCI and system address spaces. Implement these registers (though for now they have no effect since we don't implement mapping PCI space into system memory at all). The most natural order for our sysbus regions has the control registers at the start, so move all the others down one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paul Brook <paul@codesourcery.com>
2013-04-19versatile_pci: Implement the correct PCI IRQ mappingPeter Maydell1-6/+99
Implement the correct IRQ mapping for the Versatile PCI controller; it differs between realview and versatile boards, but the previous QEMU implementation was correct only for the first PCI card on a versatile board, since we weren't swizzling IRQs based on the slot number. Since this change would otherwise break any uses of PCI on Linux kernels which have an equivalent bug (since they have effectively only been tested against QEMU, not real hardware), we implement a mechanism for automatically detecting those broken kernels and switching back to the old mapping. This works by looking at the values the kernel writes to the PCI_INTERRUPT_LINE register in the config space, which is effectively the interrupt number the kernel expects the device to be using. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-19versatile_pci: Put the host bridge PCI device at slot 29Peter Maydell1-0/+2
On real hardware the host bridge appears as a PCI device in slot 29, so make QEMU put its host bridge in that slot too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paul Brook <paul@codesourcery.com>
2013-04-19versatile_pci: Use separate PCI I/O space rather than system I/O spacePeter Maydell1-4/+13
Rather than overloading the system I/O space (which doesn't even make any sense on ARM) for PCI I/O, create an memory region in the PCI controller and use that to represent the I/O space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paul Brook <paul@codesourcery.com>
2013-04-19versatile_pci: Change to subclassing TYPE_PCI_HOST_BRIDGEPeter Maydell1-11/+30
Change versatile_pci to subclass TYPE_PCI_HOST_BRIDGE and generally handle PCI in a more QOM-like fashion. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paul Brook <paul@codesourcery.com>
2013-04-19versatile_pci: Update to realize and instance init functionsPeter Maydell1-25/+25
Update the Versatile PCI controller to use a realize function rather than SysBusDevice::init. To reflect the fact that the 'realview_pci' class is taking most of its implementation from 'versatile_pci' (and to make the QOM casts work) we make 'realview_pci' a subclass of 'versatile_pci'. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paul Brook <paul@codesourcery.com>
2013-04-19versatile_pci: Expose PCI I/O region on Versatile PBPeter Maydell1-5/+3
Comments in the QEMU source code claim that the version of the PCI controller on the VersatilePB board doesn't support the PCI I/O region, but this is incorrect; expose that region, map it in the correct location, and drop the misleading comments. This change removes the only currently implemented difference between the realview-pci and versatile-pci models; however there are other differences in not-yet-implemented functionality, so we retain the distinction between the two device types. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paul Brook <paul@codesourcery.com>
2013-04-19versatile_pci: Fix hardcoded tabsPeter Maydell1-1/+1
There is just one line in this source file with a hardcoded tab indent, so just fix it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paul Brook <paul@codesourcery.com>
2013-04-08hw: move private headers to hw/ subdirectories.Paolo Bonzini2-1/+11
Many headers are used only in a single directory. These can be kept in hw/. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08hw: move PCI bridges to hw/pci-* or hw/ARCHPaolo Bonzini12-0/+4097
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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