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2022-05-15hw/openrisc: use right OMPIC size variableJason A. Donenfeld1-2/+2
2022-05-15hw/openrisc: support 4 serial ports in or1ksimJason A. Donenfeld1-6/+16
2022-05-04hw/openrisc: page-align FDT addressJason A. Donenfeld1-1/+1
2022-02-26hw/openrisc/openrisc_sim: Add support for initrd loadingStafford Horne1-0/+31
2022-02-26hw/openrisc/openrisc_sim: Add automatic device tree generationStafford Horne2-16/+175
2022-02-25hw/openrisc/openrisc_sim: Increase max_cpus to 4Stafford Horne1-3/+5
2022-02-25hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UARTStafford Horne1-8/+24
2022-02-25hw/openrisc/openrisc_sim: Parameterize initializationStafford Horne1-8/+34
2022-02-25hw/openrisc/openrisc_sim: Create machine state for or1ksimStafford Horne1-2/+28
2021-05-02Do not include exec/address-spaces.h if it's not really necessaryThomas Huth1-1/+0
2020-12-15target/openrisc: Move pic_cpu code into CPU object properPeter Maydell3-64/+2
2020-12-15hw/openrisc/openrisc_sim: Abstract out "get IRQ x of CPU y"Peter Maydell1-17/+21
2020-12-15hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUsPeter Maydell2-2/+12
2020-08-21meson: convert hw/arch*Marc-André Lureau2-2/+5
2020-06-15sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster1-2/+2
2020-06-15qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster1-4/+4
2020-06-10hw/openrisc/openrisc_sim: Add assertion to silence GCC warningPhilippe Mathieu-Daudé1-0/+1
2020-02-28hw: Make MachineClass::is_default a boolean typePhilippe Mathieu-Daudé1-1/+1
2020-01-29hw/core/loader: Let load_elf() populate a field with CPU-specific flagsAleksandar Markovic1-1/+1
2019-08-16Include hw/qdev-properties.h lessMarkus Armbruster1-0/+1
2019-08-16Include hw/hw.h exactly where neededMarkus Armbruster3-3/+0
2019-08-16Include migration/vmstate.h lessMarkus Armbruster1-0/+1
2019-08-16Include hw/irq.h a lot lessMarkus Armbruster2-0/+2
2019-08-16Include sysemu/reset.h a lot lessMarkus Armbruster1-0/+1
2019-07-05hw: Replace global smp variables with MachineState for all remaining archsLike Xu1-0/+1
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster1-1/+0
2019-05-08target/openrisc: Fix LGPL information in the file headersThomas Huth3-3/+3
2019-03-07or1k-softmmu.mak: express dependencies with KconfigPaolo Bonzini1-0/+3
2019-03-07kconfig: introduce kconfig filesPaolo Bonzini1-0/+2
2019-02-05hw/openrisc/Makefile.objs: Create CONFIG_* for openriscYang Zhong1-1/+1
2019-02-05elf: Add optional function ptr to load_elf() to parse ELF notesLiam Merwick1-1/+1
2018-04-26Change references to serial_hds[] to serial_hd()Peter Maydell1-1/+1
2018-02-06hw/openrisc: Replace fprintf(stderr, "*\n" with error_report()Alistair Francis1-2/+2
2017-10-27openrisc: use generic cpu_model parsingIgor Mammedov1-6/+2
2017-10-21openrisc: Only kick cpu on timeout, not on updateStafford Horne1-1/+1
2017-10-21openrisc: Initial SMP supportStafford Horne1-23/+65
2017-10-21openrisc/cputimer: Perparation for MulticoreStafford Horne1-15/+47
2017-09-19cpu: make cpu_generic_init() abort QEMU on errorIgor Mammedov1-4/+0
2017-09-01openrisc: replace cpu_openrisc_init() with cpu_generic_init()Igor Mammedov1-1/+1
2017-07-14hw: Use new memory_region_init_{ram, rom, rom_device}() functionsPeter Maydell1-2/+1
2017-07-14memory: Rename memory_region_init_ram() to memory_region_init_ram_nomigrate()Peter Maydell1-1/+1
2017-05-04target/openrisc: Support non-busy idle state using PMR SPRStafford Horne1-0/+1
2017-02-14target/openrisc: Rename the cpu from or32 to or1kRichard Henderson1-2/+2
2016-03-22hw: explicitly include qemu-common.h and cpu.hPaolo Bonzini1-0/+2
2016-03-22include/qemu/osdep.h: Don't include qapi/error.hMarkus Armbruster1-0/+1
2016-03-04loader: Add data swap option to load-elfPeter Crosthwaite1-1/+2
2016-01-29openrisc: Clean up includesPeter Maydell3-0/+3
2015-09-25Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-1/+1
2015-09-25openrisc: remove muldiv64()Laurent Vivier1-4/+3
2015-09-25or32: Remove ELF_MACHINE from cpu.hPeter Crosthwaite1-1/+1
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