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2011-08-08msix: convert to memory APIAvi Kivity1-42/+22
The msix table is defined as a subregion, to allow for a BAR that mixes device specific regions with the msix table. Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-07-12msix: use specific endian ld/st_physAlexander Graf1-1/+1
Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-15Merge remote-tracking branch 'origin/master' into pciMichael S. Tsirkin1-1/+1
Conflicts: hw/virtio-pci.c
2011-06-12msix: Use replace local defines with pci_regs versionsJan Kiszka1-25/+15
This also cleans up an open-coded 64-bit message address readout. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2011-05-06Fix typo in code and commentsStefan Weil1-1/+1
Replace writeable -> writable Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-01-20msix: simplify write configIsaku Yamahata1-4/+1
use pci_device_deassert_intx(). Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2010-12-11Add endianness as io mem parameterAlexander Graf1-1/+2
As stated before, devices can be little, big or native endian. The target endianness is not of their concern, so we need to push things down a level. This patch adds a parameter to cpu_register_io_memory that allows a device to choose its endianness. For now, all devices simply choose native endian, because that's the same behavior as before. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-27Merge branch 'pci' into for_anthonyMichael S. Tsirkin1-2/+6
2010-09-20msix: clear not only INTA, but all INTx when MSI-X is enabled.Isaku Yamahata1-1/+4
clear not only INTA, but all INTx when MSI-X is enabled. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2010-09-18Introduce range.hBlue Swirl1-0/+1
Extract range functions from pci.h. These will be used by later patches by non-PCI devices. Adjust current users. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-09-07pci: consolidate pci_add_capability_at_offset() into pci_add_capability().Isaku Yamahata1-1/+2
By making pci_add_capability() the special case of pci_add_capability_at_offset() of offset = 0, consolidate pci_add_capability_at_offset() into pci_add_capability(). Cc: Stefan Weil <weil@mail.berlios.de> Cc: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2010-06-14Remove unused DEBUG defines from hw/msix.cJes Sorensen1-9/+0
Remove unused DEBUG defines from hw/msix.c to avoid having anything define the word DEBUG without any additions such as MSIX_DEBUG. Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-05-31msix: remove duplicated defines.Isaku Yamahata1-8/+0
remove defines which are already defined in pci_regs.h Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-23msix: use range helper function.Isaku Yamahata1-1/+1
use range helper function in msix_write_config(). Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-07msix: function mask supportMichael S. Tsirkin1-18/+46
Function mask is a mandatory feature in MSIX spec so not implementing it is a spec violation. Implement. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-07msix: macro rename for function mask supportMichael S. Tsirkin1-7/+7
rename ENABLE_OFFSET -> CONTROL_OFFSET, since same byte includes function mask. This is in preparation for function mask support. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-01msix: clear pending bit of an unused vectorMichael S. Tsirkin1-10/+17
PCI spec states: if a masked vector has its Pending bit set, and the associated underlying interrupt events are somehow satisfied (usually by software though the exact manner is function-specific), the function must clear the Pending bit, to avoid sending a spurious interrupt message later when software unmasks the vector. In our case this happens if vector becomes unused. Clear pending bit in this case. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-01msix: fix reset value for enable bitMichael S. Tsirkin1-1/+2
On reset, we currently clear all bits in msix control register *except* enable bit. This is wrong: the spec says we should clear writeable bits: function mask and enable bit. Correct this. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-01msix: fix mask bit state after resetMichael S. Tsirkin1-0/+11
PCI spec states that mask bit must be 1 after reset. Make it so. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-01msix: add helper to unuse all msix entriesMichael S. Tsirkin1-0/+7
will be used by virtio on soft reset Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-11-09pci: introduce pcibus_t to represent pci bus address/size instead of uint32_tIsaku Yamahata1-1/+1
This patch is preliminary for 64 bit BAR support. Introduce dedicated type, pcibus_t, to represent pci bus address/size instead of uint32_t. Later this type will be changed to uint64_t. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-30qemu/msix: fix table access issuesMichael S. Tsirkin1-7/+4
Fixes a couple of issues with msix table access: - With misbehaving guests, misaligned 4 byte access could overflow msix table and cause qemu to segfault. Since PCI spec requires host to only issue dword-aligned accesses, as a fix, it's enough to mask the address low bits. - Tables use pci format, not native format, and so we must use pci_[sg]et_long on read/write. Reported-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05qemu: clean up target page usage in msixMichael S. Tsirkin1-25/+24
Since cpu_register_phys_memory does not require size to be a multiple of target page size, simply make msix page size 0x1000. Do this in msix, reverting part of 5e520a7d500ec2569d22d80f9ef4272a34cb3c80, as we no longer have to pass target page around. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-5/+5
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc1-5/+5
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-09-20Compile msix only onceBlue Swirl1-25/+25
Get page size in device init. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-25Make CPURead/WriteFunc structure 'const'Blue Swirl1-2/+2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-27qemu: msix nit: clear msix_entries_nr on errorMichael S. Tsirkin1-0/+1
I don't think it's critical to do this, but it's best to keep uninit and error recovery consistent. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-10qemu/msi: missing bracesMichael S. Tsirkin1-1/+2
MSIX present bit is tested incorrectly, and only happens to work because the bit we are testing is 0x1. Add braces to fix this. Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-10qemu/msi: clean used vectors state on loadMichael S. Tsirkin1-0/+1
Clean up msix vector usage state on load. Since guest might have control over it through the device, the device will have to load this state from file. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-09fix segfault in msix_saveMichael S. Tsirkin1-5/+7
This fixes segfault reported by Kevin Wolf, and simplifies the code in msix_save. Reported-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-05Fix Sparse warningBlue Swirl1-1/+2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-24qemu/pci: MSI-X support functionsMichael S. Tsirkin1-0/+378
Add functions implementing MSI-X support. First user will be virtio-pci. Note that platform must set a flag to declare MSI supported: this is a safety measure to avoid breaking platforms which should support MSI-X but currently lack this in the interrupt controller emulation. For PC this will be set by APIC. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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