riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2011-03-21	change all other clock references to use nanosecond resolution accessors	Paolo Bonzini	1	-5/+5
2011-01-18	mips: Expire late timers when reading cp0_count	Edgar E. Iglesias	1	-2/+10
2011-01-18	mips: Break out cpu_mips_timer_expire	Edgar E. Iglesias	1	-14/+22
2010-03-27	Compile some MIPS devices only once	Blue Swirl	1	-1/+1
2010-03-14	mips: add header to mips_int.c and mips_timer.c	Aurelien Jarno	1	-0/+22
2009-09-11	Unexport ticks_per_sec variable. Create get_ticks_per_sec() function	Juan Quintela	1	-5/+5
2009-01-15	Convert references to logfile/loglevel to use qemu_log*() macros	aliguori	1	-3/+1
2009-01-08	target-mips: CP0 Random register improvements	aurel32	1	-3/+8
2008-09-14	MIPS: remove empty cpu_mips_irqctrl_init()	aurel32	1	-4/+0
2008-06-29	Add instruction counter.	pbrook	1	-0/+5
2008-04-11	Optimize MIPS timer read/write functions	aurel32	1	-31/+25
2007-11-17	Break up vl.h.	pbrook	1	-1/+3
2007-09-25	Timer start/stop implementation, by Aurelien Jarno.	ths	1	-5/+24
2007-09-06	Partial support for 34K multithreading, not functional yet.	ths	1	-1/+1
2007-04-17	Choose number of TLBs at runtime, by Herve Poussineau.	ths	1	-1/+1
2007-04-07	Unify IRQ handling.	pbrook	1	-2/+2
2007-04-05	Fix disabling of the Cause register for R2.	ths	1	-11/+11
2007-03-18	Fix BD flag handling, cause register contents, implement some more bits	ths	1	-0/+7
2007-01-24	Reworking MIPS interrupt handling, by Aurelien Jarno.	ths	1	-4/+2
2006-12-06	Move the MIPS CPU timer in a seperate file, by Alec Voropay.	ths	1	-0/+85