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2025-03-09hw/intc/aspeed: Support setting different register sizeJamin Lin1-17/+5
Currently, the size of the regs array is 0x2000, which is too large. So far, it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000 are unused. To save code size, introduce a new class attribute "reg_size" to set the different register sizes for the INTC models in AST2700 and add a regs sub-region in the memory container. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09hw/intc/aspeed: Introduce dynamic allocation for regs arrayJamin Lin1-1/+11
Currently, the size of the "regs" array is 0x2000, which is too large. To save code size and avoid mapping large unused gaps, will update it to only map the useful set of registers. This update will support multiple sub-regions with different sizes. To address the redundant size issue, replace the static "regs" array with a dynamically allocated "regs" memory. Introduce a new "aspeed_intc_unrealize" function to free the allocated "regs" memory. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09hw/intc/aspeed: Rename status_addr and addr to status_reg and reg for clarityJamin Lin1-19/+19
Rename the variables "status_addr" to "status_reg" and "addr" to "reg" because they are used as register index. This change makes the code more appropriate and improves readability. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-09hw/intc/aspeed: Support setting different memory sizeJamin Lin1-1/+8
According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB (0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400) of register space. Introduced a new class attribute "mem_size" to set different memory sizes for the INTC models in AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-03-08exec: Declare tlb_flush*() in 'exec/cputlb.h'Philippe Mathieu-Daudé1-1/+1
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20241114011310.3615-19-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-03-05Merge tag 'pull-loongarch-20250305' of https://gitlab.com/bibo-mao/qemu into ↵Stefan Hajnoczi3-8/+155
staging loongarch queue # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCZ8ezJgAKCRAfewwSUazn # 0T9pAQCKb+C69kbf9cEVg7PU/z5I0ALFtCNWCKxSkWZPDPik4gEA3IYwdrJ+csuX # 8nWL0fzyk+8+LDzEwEgCYoNcMnttRQw= # =P8mi # -----END PGP SIGNATURE----- # gpg: Signature made Wed 05 Mar 2025 10:12:54 HKT # gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1 # gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C # Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1 * tag 'pull-loongarch-20250305' of https://gitlab.com/bibo-mao/qemu: target/loongarch: Adjust the cpu reset action to a proper position hw/loongarch/virt: Enable cpu hotplug feature on virt machine hw/loongarch/virt: Update the ACPI table for hotplug cpu hw/loongarch/virt: Implement cpu plug interface hw/loongarch/virt: Implement cpu unplug interface hw/loongarch/virt: Add basic cpu plug interface framework hw/loongarch/virt: Add topo properties on CPU object hw/loongarch/virt: Add CPU topology support hw/intc/loongarch_extioi: Use cpu plug notification hw/intc/loongarch_extioi: Implment cpu hotplug interface hw/intc/loongarch_extioi: Add basic hotplug framework hw/intc/loongarch_extioi: Move gpio irq initial to common code hw/intc/loongarch_ipi: Notify ipi object when cpu is plugged hw/intc/loongarch_ipi: Implment cpu hotplug interface hw/intc/loongarch_ipi: Add basic hotplug framework Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-05Merge tag 'pull-riscv-to-apply-20250305-1' of ↵Stefan Hajnoczi2-56/+65
https://github.com/alistair23/qemu into staging Third RISC-V PR for 10.0 * CSR coverity fixes * Fix unexpected behavior of vector reduction instructions when vl is 0 * Fix incorrect vlen comparison in prop_vlen_set * Throw debug exception before page fault * Remove redundant "hart_idx" masking from APLIC * Add support for Control Transfer Records Ext * Remove redundant struct members from the IOMMU * Remove duplicate definitions from the IOMMU * Fix tick_offset migration for Goldfish RTC * Add serial alias in virt machine DTB * Remove Bin Meng from RISC-V maintainers * Add support for Control Transfer Records Ext * Log guest errors when reserved bits are set in PTEs * Add missing Sdtrig disas CSRs * Correct the hpmevent sscofpmf mask * Mask upper sscofpmf bits during validation * Remove warnings about Smdbltrp/Smrnmi being disabled * Respect mseccfg.RLB bit for TOR mode PMP entry * Update KVM support to Linux 6.14-rc3 * IOMMU HPM support * Support Sscofpmf/Svade/Svadu/Smnpm/Ssnpm extensions in KVM * Add --ignore-family option to binfmt * Refinement for AIA with KVM acceleration * Reset time changes for KVM # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmfHrkEACgkQr3yVEwxT # gBNGTA/+N9nBPZt5cv0E/0EDZMQS8RQrQvz1yHRgAXOq8RnOdcL72v8wovGAfnVu # l0BXDoVBvw4f2Xm9Q4ptlfH8HAefCeQ4E/K9j5Lwxr8OqZHFg6e+JQIyZOt6wBWI # hJbz1/laJIbXq3cGgwcE/l0aGfb2UAAsA4dsZVt/MnjAV8GS7BF9RCkgCPxD4FZA # 0PLiq9dF+4o4q7PxnxAbUVz/uhLzqmcnQemQFHbf9Wms3tZEDKmPSoKP/v+01Rkw # tm+cgy7OocpgygbMc0nykYG50P+raUBSesk/jFGeKj8cU4IeMuzDsVPWcd4rG+0X # Z+nENfOY7vOqMCXgaQCW2r4vEQx2Gj0yQG6xmVAemRWzFHJdz5W01/uUSHzJSB+L # +VbAH55HYKr6sbgecqInQ/rsHKyw6D5QFcj/guz+kvhsH9rJ5q60uywrWL5OEuaK # vKv7cSZghlf9bwy6soassXxk8z+j4psJ7WnnVpynNKMew9yFFDhayuIFbo9952gH # 3+NCm2cQrkTYJOXAJwkxBD+I4AXxNSuxNjaVANk9q80uqbT9JiHM7pcvbJI00Fji # OutJSPYtVXEin9Ev3sJ05YQHsIcZ/Noi3O5IdaRI0AMk/8gyGyhFCVgSpV52dH59 # HguPK05e5cW/xgElGUPHrU+UtzE05p18HnSoVPclF/B5rc8QXN0= # =dobk # -----END PGP SIGNATURE----- # gpg: Signature made Wed 05 Mar 2025 09:52:01 HKT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20250305-1' of https://github.com/alistair23/qemu: (59 commits) target/riscv/kvm: add missing KVM CSRs target/riscv/kvm: add kvm_riscv_reset_regs_csr() target/riscv/cpu: remove unneeded !kvm_enabled() check hw/intc/aplic: refine kvm_msicfgaddr hw/intc/aplic: refine the APLIC realize hw/intc/imsic: refine the IMSIC realize binfmt: Add --ignore-family option binfmt: Normalize host CPU architecture binfmt: Shuffle things around target/riscv/kvm: Add some exts support docs/specs/riscv-iommu.rst: add HPM support info hw/riscv: add IOMMU HPM trace events hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap hw/riscv/riscv-iommu: add hpm events mmio write hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes hw/riscv/riscv-iommu: instantiate hpm_timer hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr() hw/riscv/riscv-iommu: add riscv-iommu-hpm file hw/riscv/riscv-iommu-bits.h: HPM bits ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-05hw/intc/loongarch_extioi: Implment cpu hotplug interfaceBibo Mao1-0/+45
When cpu is added, connect extioi gpio irq to CPU irq pin. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-03-05hw/intc/loongarch_extioi: Add basic hotplug frameworkBibo Mao1-0/+33
LoongArch extioi interrupt controller routes peripheral interrupt to multiple CPUs, physical cpu id is used in interrupt routing table. Here hotplug interface is added for extioi object, so that parent irq line can be connected, and routing table can be added for new created cpu. Here only basic hotplug framework is added, it is stub function. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-03-05hw/intc/loongarch_extioi: Move gpio irq initial to common codeBibo Mao2-8/+6
When cpu is added, it will connect gpio irq line to cpu irq. And cpu hot-add is put in common code, move gpio irq initial part into common code. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-03-05hw/intc/loongarch_ipi: Implment cpu hotplug interfaceBibo Mao1-0/+39
Add logic cpu allocation and cpu mapping with cpu hotplug interface. When cpu is added, connect ipi gpio irq to CPU IRQ_IPI irq pin. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-03-05hw/intc/loongarch_ipi: Add basic hotplug frameworkBibo Mao1-0/+32
LoongArch ipi can send interrupt to multiple CPUs, interrupt routing to CPU comes from destination physical cpu id. Here hotplug interface is added for IPI object, so that parent irq line can be connected, and routing table can be added for new created cpu. Here only basic hotplug framework is added, it is stub function. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-03-04hw/intc: Remove TCG dependency on ARM_GICV3Philippe Mathieu-Daudé2-5/+5
The TYPE_ARM_GICV3 model doesn't have any particular dependency on TCG, remove it. Rename the Kconfig selector ARM_GICV3_TCG -> ARM_GICV3. Fixes: a8a5546798c ("hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Phil Dennis-Jordan <phil@philjordan.eu> Tested-by: Phil Dennis-Jordan <phil@philjordan.eu> Message-Id: <20241227202435.48055-2-philmd@linaro.org>
2025-03-04hw/intc/aplic: refine kvm_msicfgaddrYong-Xuan Wang1-11/+13
Let kvm_msicfgaddr use the same format with mmsicfgaddr and smsicfgaddr. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250224025722.3999-4-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-04hw/intc/aplic: refine the APLIC realizeYong-Xuan Wang1-23/+26
When the APLIC is emulated in the kernel, the GPIO output lines to CPUs can be remove. In this case the APLIC trigger CPU interrupts by KVM APIs. This patch also move the code that claim the CPU interrupts to the beginning of APLIC realization. This can avoid the unnecessary resource allocation before checking failed. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250224025722.3999-3-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-04hw/intc/imsic: refine the IMSIC realizeYong-Xuan Wang1-21/+26
When the IMSIC is emulated in the kernel, the GPIO output lines to CPUs and aia_ireg_rmw_fn setting can be remove. In this case the IMSIC trigger CPU interrupts by KVM APIs, and the RMW of IREG is handled in kernel. This patch also move the code that claim the CPU interrupts to the beginning of IMSIC realization. This can avoid the unnecessary resource allocation before checking failed. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250224025722.3999-2-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-04hw/intc/riscv_aplic: Remove redundant "hart_idx" maskingHuang Borong1-1/+0
Remove the redundant masking of "hart_idx", as the same operation is performed later during address calculation. This change impacts the "hart_idx" value in the final qemu_log_mask() call. The original "hart_idx" parameter should be used for logging to ensure accuracy, rather than the masked value. Signed-off-by: Huang Borong <huangborong@bosc.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20250115035105.19600-1-huangborong@bosc.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-02-20hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64()Peter Maydell1-3/+3
In the gicv3_{irq,fiq,irqfiq}_access() functions, in the arm_current_el(env) == 3 case we do the following test: if (!is_a64(env) && !arm_is_el3_or_mon(env)) { r = CP_ACCESS_TRAP_EL3; } In this check, the "!is_a64(env)" is redundant, because if we are at EL3 and in AArch64 then arm_is_el3_or_mon() will return true and we will skip the if() body anyway. Remove the unnecessary tests. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250130182309.717346-9-peter.maydell@linaro.org
2025-02-20hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3Peter Maydell1-9/+0
In the gicv3_{irq,fiq,irqfiq}_access() functions, there is a check which downgrades a CP_ACCESS_TRAP_EL3 to CP_ACCESS_TRAP if EL3 is not AArch64. This has been there since the GIC was first implemented, but it isn't right: if we are trapping because of SCR.IRQ or SCR.FIQ then we definitely want to be going to EL3 (doing AArch32.TakeMonitorTrapException() in pseudocode terms). We might want to not take a trap at all, but we don't ever want to go to the default target EL, because that would mean, for instance, taking a trap to Hyp mode if the trapped access was made from Hyp mode. (This might have been an attempt to work around our failure to properly implement Monitor Traps.) Remove the bogus check. Cc: qemu-stable@nongnu.org Fixes: 359fbe65e01e ("hw/intc/arm_gicv3: Implement GICv3 CPU interface registers") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250130182309.717346-7-peter.maydell@linaro.org
2025-02-16hw/arm: Mark Allwinner Technology devices as little-endianPhilippe Mathieu-Daudé1-1/+1
These devices are only used by the ARM targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250212113938.38692-2-philmd@linaro.org>
2025-02-16hw/intc/xilinx_intc: Make device endianness configurablePhilippe Mathieu-Daudé1-13/+44
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "endianness" property to select the device endianness. This property is unspecified by default, and machines need to set it explicitly. Set the proper endianness for each machine using the device. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250213122217.62654-3-philmd@linaro.org>
2025-02-16hw/intc/apic: Fixes magic number use, removes outdated commentPhil Dennis-Jordan1-2/+1
This changes replaces the use of an explicit literal constant for the APIC base address mask with the existing symbolic constant intended for this purpose. Additionally, we remove the comment about not being able to re-enable the APIC after disabling it. This is no longer the case after the APIC implementation's state machine was modified in 9.0. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241209203629.74436-11-phil@philjordan.eu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-01-15hw/intc/loongarch_ipi: Use alternative implemation for cpu_by_arch_idBibo Mao1-25/+11
There is arch_id and CPUState pointer in IPICore object. With function cpu_by_arch_id() it can be implemented by parsing IPICore array inside, rather than possible_cpus array. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-01-15hw/intc/loongson_ipi: Add more input parameter for cpu_by_arch_idBibo Mao3-14/+49
Add logic cpu index input parameter for function cpu_by_arch_id, CPUState::cpu_index is logic cpu slot index for possible_cpus. At the same time it is logic index with LoongsonIPICommonState::IPICore, here hide access for CPUState::cpu_index directly, it comes from function cpu_by_arch_id(). Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-01-15hw/intc/loongarch_ipi: Remove property num-cpuBibo Mao1-5/+0
Since cpu number can be acquired from possible_cpu_arch_ids(), num-cpu property is not necessary. Here remove num-cpu property for object TYPE_LOONGARCH_IPI object. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-01-15hw/intc/loongarch_ipi: Get cpu number from possible_cpu_arch_idsBibo Mao1-5/+8
Supported CPU number can be acquired from function possible_cpu_arch_ids(), cpu-num property is not necessary and can be removed. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-01-15hw/intc/loongson_ipi: Remove property num_cpu from loongson_ipi_commonBibo Mao3-6/+12
With mips64 loongson ipi, num_cpu property is used. With loongarch ipi, num_cpu can be acquired from possible_cpu_arch_ids. Here remove property num_cpu from loongson_ipi_common, and put it into loongson and loongarch ipi separately. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-01-15hw/intc/loongson_ipi: Remove num_cpu from loongson_ipi_commonBibo Mao3-15/+26
With mips64 loongson ipi, num_cpu property is used. With loongarch ipi, num_cpu can be acquired from possible_cpu_arch_ids. Here remove num_cpu setting from loongson_ipi_common, and this piece of code is put into loongson and loongarch ipi separately. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-01-15hw/intc/loongarch_ipi: Implement realize interfaceBibo Mao1-0/+19
Add realize interface for loongarch ipi device. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-01-13hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bitPhilippe Mathieu-Daudé1-0/+4
All these MemoryRegionOps read() and write() handlers are implemented expecting 32-bit accesses. Clarify that setting .impl.min/max_access_size fields. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20241105130431.22564-8-philmd@linaro.org>
2025-01-09hw/intc/loongarch_extioi: Add irq routing support from physical idBibo Mao1-4/+26
The simliar with IPI interrupt controller, physical cpu id is used for irq routing for extioi interrupt controller. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-01-09hw/intc/loongarch_extioi: Remove num-cpu propertyBibo Mao1-1/+0
Since cpu number can be acquired from possible_cpu_arch_ids(), num-cpu property is not necessary. Here remove num-cpu property for object TYPE_LOONGARCH_EXTIOI_COMMON object. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-01-09hw/intc/loongarch_extioi: Get cpu number from possible_cpu_arch_idsBibo Mao2-8/+15
Supported CPU number can be acquired from function possible_cpu_arch_ids(), cpu-num property is not necessary. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-01-07hw/s390x: Remove the "adapter_routes_max_batch" property from the flicThomas Huth1-9/+0
Now that the s390-ccw-virtio-2.8 machine has been removed, we don't need the "adapter_routes_max_batch" property anymore and can remove it. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Acked-by: Christian Borntraeger <borntraeger@linux.ibm.com> Message-ID: <20250103144232.520383-11-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-12-21Merge tag 'exec-20241220' of https://github.com/philmd/qemu into stagingStefan Hajnoczi27-49/+49
Accel & Exec patch queue - Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander) - Add '-d invalid_mem' logging option (Zoltan) - Create QOM containers explicitly (Peter) - Rename sysemu/ -> system/ (Philippe) - Re-orderning of include/exec/ headers (Philippe) Move a lot of declarations from these legacy mixed bag headers: . "exec/cpu-all.h" . "exec/cpu-common.h" . "exec/cpu-defs.h" . "exec/exec-all.h" . "exec/translate-all" to these more specific ones: . "exec/page-protection.h" . "exec/translation-block.h" . "user/cpu_loop.h" . "user/guest-host.h" . "user/page-protection.h" # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmdlnyAACgkQ4+MsLN6t # wN6mBw//QFWi7CrU+bb8KMM53kOU9C507tjn99LLGFb5or73/umDsw6eo/b8DHBt # KIwGLgATel42oojKfNKavtAzLK5rOrywpboPDpa3SNeF1onW+99NGJ52LQUqIX6K # A6bS0fPdGG9ZzEuPpbjDXlp++0yhDcdSgZsS42fEsT7Dyj5gzJYlqpqhiXGqpsn8 # 4Y0UMxSL21K3HEexlzw2hsoOBFA3tUm2ujNDhNkt8QASr85yQVLCypABJnuoe/// # 5Ojl5wTBeDwhANET0rhwHK8eIYaNboiM9fHopJYhvyw1bz6yAu9jQwzF/MrL3s/r # xa4OBHBy5mq2hQV9Shcl3UfCQdk/vDaYaWpgzJGX8stgMGYfnfej1SIl8haJIfcl # VMX8/jEFdYbjhO4AeGRYcBzWjEJymkDJZoiSWp2NuEDi6jqIW+7yW1q0Rnlg9lay # ShAqLK5Pv4zUw3t0Jy3qv9KSW8sbs6PQxtzXjk8p97rTf76BJ2pF8sv1tVzmsidP # 9L92Hv5O34IqzBu2oATOUZYJk89YGmTIUSLkpT7asJZpBLwNM2qLp5jO00WVU0Sd # +kAn324guYPkko/TVnjC/AY7CMu55EOtD9NU35k3mUAnxXT9oDUeL4NlYtfgrJx6 # x1Nzr2FkS68+wlPAFKNSSU5lTjsjNaFM0bIJ4LCNtenJVP+SnRo= # =cjz8 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Dec 2024 11:45:20 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'exec-20241220' of https://github.com/philmd/qemu: (59 commits) util/qemu-timer: fix indentation meson: Do not define CONFIG_DEVICES on user emulation system/accel-ops: Remove unnecessary 'exec/cpu-common.h' header system/numa: Remove unnecessary 'exec/cpu-common.h' header hw/xen: Remove unnecessary 'exec/cpu-common.h' header target/mips: Drop left-over comment about Jazz machine target/mips: Remove tswap() calls in semihosting uhi_fstat_cb() target/xtensa: Remove tswap() calls in semihosting simcall() helper accel/tcg: Un-inline translator_is_same_page() accel/tcg: Include missing 'exec/translation-block.h' header accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h' accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h' qemu/coroutine: Include missing 'qemu/atomic.h' header exec/translation-block: Include missing 'qemu/atomic.h' header accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h' exec/cpu-all: Include 'cpu.h' earlier so MMU_USER_IDX is always defined target/sparc: Move sparc_restore_state_to_opc() to cpu.c target/sparc: Uninline cpu_get_tb_cpu_state() target/loongarch: Declare loongarch_cpu_dump_state() locally user: Move various declarations out of 'exec/exec-all.h' ... Conflicts: hw/char/riscv_htif.c hw/intc/riscv_aplic.c target/s390x/cpu.c Apply sysemu header path changes to not in the pull request. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-21Merge tag 'pull-riscv-to-apply-20241220' of ↵Stefan Hajnoczi1-14/+60
https://github.com/alistair23/qemu into staging RISC-V PR for 10.0 * Correct the validness check of iova * Fix APLIC in_clrip and clripnum write emulation * Support riscv-iommu-sys device * Add Tenstorrent Ascalon CPU * Add AIA userspace irqchip_split support * Add Microblaze V generic board * Upgrade ACPI SPCR table to support SPCR table revision 4 format * Remove tswap64() calls from HTIF * Support 64-bit address of initrd * Introduce svukte ISA extension * Support ssstateen extension * Support for RV64 Xiangshan Nanhu CPU # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmdkzjgACgkQr3yVEwxT # gBOcyA//e0XhAQciQglCZZCfINdOyI8qSh+P2K0qtrXZ4VERHEMp7UoD5CQr2cZv # h8ij1EkatXCwukVELx0rNckxG33bEFgG1oESnQSrwGE0Iu4csNW24nK5WlUS0/r+ # A5oD2wtzEF+cbhTKrVSDBN/PvlnWTKGEoJRkuXWfz5d4uR9eyQhfED0S2j36lNEC # X1x/OZoKM89XuXtOFe9g55Z5UNzAatcdTISozL0FydiPh7QeVjTLHh28/tt559MX # 7v5aJFlQuZ78z1mIHkZmPSorSrJ0zqhkP6NWe1ae06oMgzwRQQhYLppDILV4ZgUF # 3mSDRoXmBycQXiYNPcHep3LdXfvxr+PpWHSevx8gH1jwm93On7Y/H7Uol6TDXzfC # mrFjalfV5tzrD90ZvB+s5bCMF1q5Z8Dlj0pYF9aN9P1ILoWy3dndFAPJB6uKKDP7 # Qd4qOQ3dVyHAX9jLmVkB6QvAV/vTDrYTsAxaF/EaoLOy0IoKhjTvgda3XzE1MFKA # gVafLluADIfSEdqa2QR2ExL8d1SZVoiObCp5TMLRer0HIpg/vQZwjfdbo4BgQKL3 # 7Q6wBxcZUNqrFgspXjm5WFIrdk2rfS/79OmvpNM6SZaK6BnklntdJHJHtAWujGsm # EM310AUFpHMp2h6Nqnemb3qr5l4d20KSt8DhoPAUq1IE59Kb8XY= # =0iQW # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Dec 2024 20:54:00 EST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20241220' of https://github.com/alistair23/qemu: (39 commits) target/riscv: add support for RV64 Xiangshan Nanhu CPU target/riscv: add ssstateen target/riscv/tcg: hide warn for named feats when disabling via priv_ver target/riscv: Include missing headers in 'internals.h' target/riscv: Include missing headers in 'vector_internals.h' target/riscv: Check svukte is not enabled in RV32 target/riscv: Expose svukte ISA extension target/riscv: Check memory access to meet svukte rule target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled target/riscv: Add svukte extension capability variable hw/riscv: Add the checking if DTB overlaps to kernel or initrd hw/riscv: Add a new struct RISCVBootInfo hw/riscv: Support to load DTB after 3GB memory on 64-bit system. hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses hw/char/riscv_htif: Explicit little-endian implementation MAINTAINERS: Cover RISC-V HTIF interface tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format qtest: allow SPCR acpi table changes ... Conflicts: target/riscv/cpu.c Merge conflict with DEFINE_PROP_END_OF_LIST() removal. No Property array terminator is needed anymore. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-21Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi38-45/+0
* qdev: second part of Property cleanups * rust: second part of QOM rework * rust: callbacks wrapper * rust: pl011 bugfixes * kvm: cleanup errors in kvm_convert_memory() # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmdkaEkUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroN0/wgAgIJg8BrlRKfmiz14NZfph8/jarSj # TOWYVxL2v4q98KBuL5pta2ucObgzwqyqSyc02S2DGSOIMQCIiBB5MaCk1iMjx+BO # pmVU8gNlD8faO8SSmnnr+jDQt+G+bQ/nRgQJOAReF8oVw3O2aC/FaVKpitMzWtvv # PLnJWdrqqpGq14OzX8iNCzSujxppAuyjrhT4lNlekzDoDfdTez72r+rXkvg4GzZL # QC3xLYg/LrT8Rs+zgOhm/AaIyS4bOyMlkU9Du1rQ6Tyne45ey2FCwKVzBKrJdGcw # sVbzEclxseLenoTbZqYK6JTzLdDoThVUbY2JwoCGUaIm+74P4NjEsUsTVg== # =TuQM # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Dec 2024 13:39:05 EST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (42 commits) rust: pl011: simplify handling of the FIFO enabled bit in LCR rust: pl011: fix migration stream rust: pl011: extend registers to 32 bits rust: pl011: fix break errors and definition of Data struct rust: pl011: always use reset() method on registers rust: pl011: match break logic of C version rust: pl011: fix declaration of LineControl bits target/i386: Reset TSCs of parked vCPUs too on VM reset kvm: consistently return 0/-errno from kvm_convert_memory rust: qemu-api: add a module to wrap functions and zero-sized closures rust: qom: add initial subset of methods on Object rust: qom: add casting functionality rust: tests: allow writing more than one test bql: add a "mock" BQL for Rust unit tests rust: re-export C types from qemu-api submodules rust: rename qemu-api modules to follow C code a bit more rust: qom: add possibility of overriding unparent rust: qom: put class_init together from multiple ClassInitImpl<> Constify all opaque Property pointers hw/core/qdev-properties: Constify Property argument to PropertyInfo.print ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-20include: Rename sysemu/ -> system/Philippe Mathieu-Daudé27-48/+48
Headers in include/sysemu/ are not only related to system *emulation*, they are also used by virtualization. Rename as system/ which is clearer. Files renamed manually then mechanical change using sed tool. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Message-Id: <20241203172445.28576-1-philmd@linaro.org>
2024-12-20hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsicDaniel Henrique Barboza1-9/+33
The last step to enable KVM AIA aplic-imsic with irqchip in split mode is to deal with how MSIs are going to be sent. In our current design we don't allow an APLIC controller to send MSIs unless it's on m-mode. And we also do not allow Supervisor MSI address configuration via the 'smsiaddrcfg' and 'smsiaddrcfgh' registers unless it's also a m-mode APLIC controller. Add a new RISCVACPLICState attribute called 'kvm_msicfgaddr'. This attribute represents the base configuration address for MSIs, in our case the base addr of the IMSIC controller. This attribute is being set only when running irqchip_split() mode with aia=aplic-imsic. During riscv_aplic_msi_send() we'll check if the attribute was set to skip the check for a m-mode APLIC controller and to change the resulting MSI addr by adding kvm_msicfgaddr right before address_space_stl_le(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241119191706.718860-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-12-20hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpersDaniel Henrique Barboza1-3/+21
The current logic to determine if we don't need an emulated APLIC controller, i.e. KVM will provide for us, is to determine if we're running KVM, with in-kernel irqchip support, and running aia=aplic-imsic. This is modelled by riscv_is_kvm_aia_aplic_imsic() and virt_use_kvm_aia_aplic_imsic(). This won't suffice to support irqchip_split() mode: it will match exactly the same conditions as the one above, but setting the irqchip to 'split' mode will now require us to emulate an APLIC s-mode controller, like we're doing with 'aia=aplic'. Create a new riscv_use_emulated_aplic() helper that will encapsulate this logic. Replace the uses of "riscv_is_kvm_aia_aplic_imsic()" with this helper every time we're taking a decision on emulate an APLIC controller or not. Do the same in virt.c with virt_use_emulated_aplic(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241119191706.718860-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-12-20hw/intc/riscv_aplic: rename is_kvm_aia()Daniel Henrique Barboza1-4/+4
The helper is_kvm_aia() is checking not only for AIA, but for aplic-imsic (i.e. "aia=aplic-imsic" in 'virt' RISC-V machine) with an in-kernel chip present. Rename it to be a bit clear what the helper is doing since we'll add more AIA helpers in the next patches. Make the helper public because the 'virt' machine will use it as well. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241119191706.718860-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-12-20hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulationYong-Xuan Wang1-1/+5
In the section "4.7 Precise effects on interrupt-pending bits" of the RISC-V AIA specification defines that: "If the source mode is Level1 or Level0 and the interrupt domain is configured in MSI delivery mode (domaincfg.DM = 1): The pending bit is cleared whenever the rectified input value is low, when the interrupt is forwarded by MSI, or by a relevant write to an in_clrip register or to clripnum." Update the riscv_aplic_set_pending() to match the spec. Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode") Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241029085349.30412-1-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-12-19Merge tag 'pull-loongarch-20241219' of https://gitlab.com/bibo-mao/qemu into ↵Stefan Hajnoczi5-148/+284
staging loongarch queue # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCZ2PKBQAKCRAfewwSUazn # 0QAZAQCxbLnvzOb9TPORlg5w0n/xFaKCL7dJbJE4WjlM7dhLkAEA5G8JVoP5Ju2B # mcK7wbymyXNX1ocsukL/JM2JavHS+AI= # =JoSk # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Dec 2024 02:23:49 EST # gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1 # gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C # Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1 * tag 'pull-loongarch-20241219' of https://gitlab.com/bibo-mao/qemu: hw/intc/loongarch_extioi: Code cleanup about loongarch_extioi hw/intc/loongarch_extioi: Add pre_save interface hw/intc/loongarch_extioi: Inherit from loongarch_extioi_common hw/intc/loongarch_extioi: Add common file loongarch_extioi_common hw/intc/loongarch_extioi: Add unrealize interface hw/intc/loongarch_extioi: Add common realize interface hw/intc/loongarch_extioi: Rename LoongArchExtIOI with LoongArchExtIOICommonState include: Rename LoongArchExtIOI with LoongArchExtIOICommonState include: Move struct LoongArchExtIOI to header file loongarch_extioi_common include: Add loongarch_extioi_common header file hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic hw/intc/loongarch_pch: Add pre_save and post_load interfaces hw/intc/loongarch_pch: Inherit from loongarch_pic_common hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState hw/intc/loongarch_pch: Merge instance_init() into realize() include: Move struct LoongArchPCHPIC to loongarch_pic_common header file include: Add loongarch_pic_common header file Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-19include/hw/qdev-properties: Remove DEFINE_PROP_END_OF_LISTRichard Henderson38-45/+0
Now that all of the Property arrays are counted, we can remove the terminator object from each array. Update the assertions in device_class_set_props to match. With struct Property being 88 bytes, this was a rather large form of terminator. Saves 30k from qemu-system-aarch64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-21-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19hw/intc/loongarch_extioi: Code cleanup about loongarch_extioiBibo Mao1-17/+14
Remove definition about LoongArchExtIOI and LOONGARCH_EXTIOI, and replace them with LoongArchExtIOICommonState and macro LOONGARCH_EXTIOI_COMMON separately. Also remove unnecessary header files. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19hw/intc/loongarch_extioi: Add pre_save interfaceBibo Mao1-0/+13
Add vmstate pre_save interface, which can be used extioi kvm driver in future. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19hw/intc/loongarch_extioi: Inherit from loongarch_extioi_commonBibo Mao3-22/+58
Set TYPE_LOONGARCH_EXTIOI inherit from TYPE_LOONGARCH_EXTIOI_COMMON object, it shares vmsate and property of TYPE_LOONGARCH_EXTIOI_COMMON, and has its own realize() function. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19hw/intc/loongarch_extioi: Add common file loongarch_extioi_commonBibo Mao2-57/+65
Add new common file loongarch_extioi_common.c, and move vmstate and property structure to common file. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19hw/intc/loongarch_extioi: Add unrealize interfaceBibo Mao1-3/+3
For loongarch extioi emulation driver, add unrealize interface and remove instance_finalize interface and move the code to unrealize interface. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19hw/intc/loongarch_extioi: Add common realize interfaceBibo Mao1-2/+14
Add common realize function, it is only to check validity of property. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
generated by cgit v1.1 at 2025-09-20 06:38:59 +0000